Reconfigurable adaptive FEC system with interleaving

Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes a reconfigurable adaptive FEC system with interleaving. For adaptive FEC schemes, we can implement an optimal RS decoder composed of minimum hardware units for any given error correction capability t. If the hardware units of the RS decoder can be reduced for any given t, we can embed as large deinterleaver as possible into the RS decoder for each t. Reconfiguring the RS decoder embedded with the expanded deinterleaver dynamically for each t allows us to decode larger interleaved codes which are more robust FEC codes to burst errors. Our reconfigurable adaptive FEC system with interleaving achieves better packet error rate and higher throughput than fixed hardware systems.

Original languageEnglish
Title of host publicationProceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Pages1252-1255
Number of pages4
Publication statusPublished - 2005 Dec 1
Event2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China
Duration: 2005 Jan 182005 Jan 21

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2

Conference

Conference2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
CountryChina
CityShanghai
Period05/1/1805/1/21

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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