Reconfigurable adaptive FEC system with interleaving

Kazunori Shimizu; Nozomu Togawa; Takeshi Ikenaga; Satoshi Goto

Reconfigurable adaptive FEC system with interleaving

Kazunori Shimizu^*, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper proposes a reconfigurable adaptive FEC system with interleaving. For adaptive FEC schemes, we can implement an optimal RS decoder composed of minimum hardware units for any given error correction capability t. If the hardware units of the RS decoder can be reduced for any given t, we can embed as large deinterleaver as possible into the RS decoder for each t. Reconfiguring the RS decoder embedded with the expanded deinterleaver dynamically for each t allows us to decode larger interleaved codes which are more robust FEC codes to burst errors. Our reconfigurable adaptive FEC system with interleaving achieves better packet error rate and higher throughput than fixed hardware systems.

Original language	English
Title of host publication	Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Pages	1252-1255
Number of pages	4
Publication status	Published - 2005 Dec 1
Event	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China Duration: 2005 Jan 18 → 2005 Jan 21

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	2

Conference

Conference	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Country/Territory	China
City	Shanghai
Period	05/1/18 → 05/1/21

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Cite this

Reconfigurable adaptive FEC system with interleaving. / Shimizu, Kazunori; Togawa, Nozomu ; Ikenaga, Takeshi et al.

Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. 2005. p. 1252-1255 1466570 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shimizu, K, Togawa, N , Ikenaga, T & Goto, S 2005, Reconfigurable adaptive FEC system with interleaving. in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005., 1466570, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2, pp. 1252-1255, 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai, China, 05/1/18.

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AB - This paper proposes a reconfigurable adaptive FEC system with interleaving. For adaptive FEC schemes, we can implement an optimal RS decoder composed of minimum hardware units for any given error correction capability t. If the hardware units of the RS decoder can be reduced for any given t, we can embed as large deinterleaver as possible into the RS decoder for each t. Reconfiguring the RS decoder embedded with the expanded deinterleaver dynamically for each t allows us to decode larger interleaved codes which are more robust FEC codes to burst errors. Our reconfigurable adaptive FEC system with interleaving achieves better packet error rate and higher throughput than fixed hardware systems.

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Reconfigurable adaptive FEC system with interleaving

Abstract

Publication series

Conference

ASJC Scopus subject areas

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