Reconfigurable circuit design based on arithmetic logic unit using double-gate cntfets

Hiroshi Ninomiya, Manabu Kobayashi, Yasuyuki Miura, Shigeyoshi Watanabe

Research output: Contribution to journalArticle

Abstract

This letter describes a design methodology for an arithmetic logic unit (ALU) incorporating reconfigurability based on doublegate carbon nanotube field-effect transistors (DG-CNTFETs). The design of a DG-CNTFET with an ambipolar-property-based reconfigurable static logic circuit is simple and straightforward using an ambipolar binary decision diagram (Am-BDD), which represents the cornerstone for the automatic pass transistor logic (PTL) synthesis flows of ambipolar devices. In this work, an ALU with 16 functions is synthesized by the design methodology of a DG-CNTFET-based reconfigurable static logic circuit. Furthermore, it is shown that the proposed ALU is much more flexible and practical than a conventional DG-CNTFET-based reconfigurable ALU.

Original languageEnglish
Pages (from-to)675-678
Number of pages4
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE97-A
Issue number2
DOIs
Publication statusPublished - 2014 Jan 1
Externally publishedYes

Fingerprint

Carbon nanotube field effect transistors
Circuit Design
Field-effect Transistor
Logic
Nanotubes
Unit
Networks (circuits)
Logic circuits
Carbon
Binary decision diagrams
Design Methodology
Logic Synthesis
Reconfigurability
Transistors
Decision Diagrams
Binary

Keywords

  • Ambipolar device
  • Arithmetic logic unit
  • Binary decision diagram
  • Doublegate CNTFET
  • Reconfigurable logic circuit design

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

Reconfigurable circuit design based on arithmetic logic unit using double-gate cntfets. / Ninomiya, Hiroshi; Kobayashi, Manabu; Miura, Yasuyuki; Watanabe, Shigeyoshi.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E97-A, No. 2, 01.01.2014, p. 675-678.

Research output: Contribution to journalArticle

@article{f9c6e46b46b84f1199d2b5fda0cf2b54,
title = "Reconfigurable circuit design based on arithmetic logic unit using double-gate cntfets",
abstract = "This letter describes a design methodology for an arithmetic logic unit (ALU) incorporating reconfigurability based on doublegate carbon nanotube field-effect transistors (DG-CNTFETs). The design of a DG-CNTFET with an ambipolar-property-based reconfigurable static logic circuit is simple and straightforward using an ambipolar binary decision diagram (Am-BDD), which represents the cornerstone for the automatic pass transistor logic (PTL) synthesis flows of ambipolar devices. In this work, an ALU with 16 functions is synthesized by the design methodology of a DG-CNTFET-based reconfigurable static logic circuit. Furthermore, it is shown that the proposed ALU is much more flexible and practical than a conventional DG-CNTFET-based reconfigurable ALU.",
keywords = "Ambipolar device, Arithmetic logic unit, Binary decision diagram, Doublegate CNTFET, Reconfigurable logic circuit design",
author = "Hiroshi Ninomiya and Manabu Kobayashi and Yasuyuki Miura and Shigeyoshi Watanabe",
year = "2014",
month = "1",
day = "1",
doi = "10.1587/transfun.E97.A.675",
language = "English",
volume = "E97-A",
pages = "675--678",
journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
issn = "0916-8508",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "2",

}

TY - JOUR

T1 - Reconfigurable circuit design based on arithmetic logic unit using double-gate cntfets

AU - Ninomiya, Hiroshi

AU - Kobayashi, Manabu

AU - Miura, Yasuyuki

AU - Watanabe, Shigeyoshi

PY - 2014/1/1

Y1 - 2014/1/1

N2 - This letter describes a design methodology for an arithmetic logic unit (ALU) incorporating reconfigurability based on doublegate carbon nanotube field-effect transistors (DG-CNTFETs). The design of a DG-CNTFET with an ambipolar-property-based reconfigurable static logic circuit is simple and straightforward using an ambipolar binary decision diagram (Am-BDD), which represents the cornerstone for the automatic pass transistor logic (PTL) synthesis flows of ambipolar devices. In this work, an ALU with 16 functions is synthesized by the design methodology of a DG-CNTFET-based reconfigurable static logic circuit. Furthermore, it is shown that the proposed ALU is much more flexible and practical than a conventional DG-CNTFET-based reconfigurable ALU.

AB - This letter describes a design methodology for an arithmetic logic unit (ALU) incorporating reconfigurability based on doublegate carbon nanotube field-effect transistors (DG-CNTFETs). The design of a DG-CNTFET with an ambipolar-property-based reconfigurable static logic circuit is simple and straightforward using an ambipolar binary decision diagram (Am-BDD), which represents the cornerstone for the automatic pass transistor logic (PTL) synthesis flows of ambipolar devices. In this work, an ALU with 16 functions is synthesized by the design methodology of a DG-CNTFET-based reconfigurable static logic circuit. Furthermore, it is shown that the proposed ALU is much more flexible and practical than a conventional DG-CNTFET-based reconfigurable ALU.

KW - Ambipolar device

KW - Arithmetic logic unit

KW - Binary decision diagram

KW - Doublegate CNTFET

KW - Reconfigurable logic circuit design

UR - http://www.scopus.com/inward/record.url?scp=84893335087&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84893335087&partnerID=8YFLogxK

U2 - 10.1587/transfun.E97.A.675

DO - 10.1587/transfun.E97.A.675

M3 - Article

AN - SCOPUS:84893335087

VL - E97-A

SP - 675

EP - 678

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 2

ER -