Reconfigurable fault tolerant binary tree - implementation in two-dimensional arrays and reliability analysis -

Ituso Takanami, Katsushi Inoue, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

We propose a reconfiguration scheme of repairing faulty processors where processors on each level of a binary tree are considered to be a linear array in which spare processors are inserted at regular intervals. The switching networks for compensation are regular and comparatively simple. The logic circuits are simple and their switchings for repair are done autonomously. We give a method of embedding the proposed tree architectures into two-dimensional arrays for WSI implementations. The method embeds the PE's from the root to a certain level L0 into a rectangular array, which is called a root module. For levels L(>L0), the linear array on each level is partitioned into subarrays. Such subarrays are called level modules. A binary tree-connected computer with a specified height is constructed by embedding these modules into two-dimensional arrays. Next, for the proposed scheme. We derive the necessary and sufficient condition for reconfigurability. Using the result, we obtain a formula for computing system's reliability. The reliabilities of our systems are compared with those of several systems already known, and the effectiveness of our systems is shown.

Original languageEnglish
Title of host publication1994 IEEE International Conference on Wafer Scale Integration
EditorsMike R. Lea, Stuart Tewksbury
Place of PublicationPiscataway, NJ, United States
PublisherPubl by IEEE
Pages132-142
Number of pages11
ISBN (Print)0780318501
Publication statusPublished - 1994
Externally publishedYes
EventProceedings of the 6th Annual IEEE International Conference on Wafer Scale Integration - San Francisco, CA, USA
Duration: 1994 Jan 191994 Jan 21

Other

OtherProceedings of the 6th Annual IEEE International Conference on Wafer Scale Integration
CitySan Francisco, CA, USA
Period94/1/1994/1/21

Fingerprint

Binary trees
Reliability analysis
Logic circuits
Switching networks
Repair
Compensation and Redress

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Takanami, I., Inoue, K., & Watanabe, T. (1994). Reconfigurable fault tolerant binary tree - implementation in two-dimensional arrays and reliability analysis -. In M. R. Lea, & S. Tewksbury (Eds.), 1994 IEEE International Conference on Wafer Scale Integration (pp. 132-142). Piscataway, NJ, United States: Publ by IEEE.

Reconfigurable fault tolerant binary tree - implementation in two-dimensional arrays and reliability analysis -. / Takanami, Ituso; Inoue, Katsushi; Watanabe, Takahiro.

1994 IEEE International Conference on Wafer Scale Integration. ed. / Mike R. Lea; Stuart Tewksbury. Piscataway, NJ, United States : Publ by IEEE, 1994. p. 132-142.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Takanami, I, Inoue, K & Watanabe, T 1994, Reconfigurable fault tolerant binary tree - implementation in two-dimensional arrays and reliability analysis -. in MR Lea & S Tewksbury (eds), 1994 IEEE International Conference on Wafer Scale Integration. Publ by IEEE, Piscataway, NJ, United States, pp. 132-142, Proceedings of the 6th Annual IEEE International Conference on Wafer Scale Integration, San Francisco, CA, USA, 94/1/19.
Takanami I, Inoue K, Watanabe T. Reconfigurable fault tolerant binary tree - implementation in two-dimensional arrays and reliability analysis -. In Lea MR, Tewksbury S, editors, 1994 IEEE International Conference on Wafer Scale Integration. Piscataway, NJ, United States: Publ by IEEE. 1994. p. 132-142
Takanami, Ituso ; Inoue, Katsushi ; Watanabe, Takahiro. / Reconfigurable fault tolerant binary tree - implementation in two-dimensional arrays and reliability analysis -. 1994 IEEE International Conference on Wafer Scale Integration. editor / Mike R. Lea ; Stuart Tewksbury. Piscataway, NJ, United States : Publ by IEEE, 1994. pp. 132-142
@inproceedings{fe886aad9d8c4f94a7d60eee2bba4920,
title = "Reconfigurable fault tolerant binary tree - implementation in two-dimensional arrays and reliability analysis -",
abstract = "We propose a reconfiguration scheme of repairing faulty processors where processors on each level of a binary tree are considered to be a linear array in which spare processors are inserted at regular intervals. The switching networks for compensation are regular and comparatively simple. The logic circuits are simple and their switchings for repair are done autonomously. We give a method of embedding the proposed tree architectures into two-dimensional arrays for WSI implementations. The method embeds the PE's from the root to a certain level L0 into a rectangular array, which is called a root module. For levels L(>L0), the linear array on each level is partitioned into subarrays. Such subarrays are called level modules. A binary tree-connected computer with a specified height is constructed by embedding these modules into two-dimensional arrays. Next, for the proposed scheme. We derive the necessary and sufficient condition for reconfigurability. Using the result, we obtain a formula for computing system's reliability. The reliabilities of our systems are compared with those of several systems already known, and the effectiveness of our systems is shown.",
author = "Ituso Takanami and Katsushi Inoue and Takahiro Watanabe",
year = "1994",
language = "English",
isbn = "0780318501",
pages = "132--142",
editor = "Lea, {Mike R.} and Stuart Tewksbury",
booktitle = "1994 IEEE International Conference on Wafer Scale Integration",
publisher = "Publ by IEEE",

}

TY - GEN

T1 - Reconfigurable fault tolerant binary tree - implementation in two-dimensional arrays and reliability analysis -

AU - Takanami, Ituso

AU - Inoue, Katsushi

AU - Watanabe, Takahiro

PY - 1994

Y1 - 1994

N2 - We propose a reconfiguration scheme of repairing faulty processors where processors on each level of a binary tree are considered to be a linear array in which spare processors are inserted at regular intervals. The switching networks for compensation are regular and comparatively simple. The logic circuits are simple and their switchings for repair are done autonomously. We give a method of embedding the proposed tree architectures into two-dimensional arrays for WSI implementations. The method embeds the PE's from the root to a certain level L0 into a rectangular array, which is called a root module. For levels L(>L0), the linear array on each level is partitioned into subarrays. Such subarrays are called level modules. A binary tree-connected computer with a specified height is constructed by embedding these modules into two-dimensional arrays. Next, for the proposed scheme. We derive the necessary and sufficient condition for reconfigurability. Using the result, we obtain a formula for computing system's reliability. The reliabilities of our systems are compared with those of several systems already known, and the effectiveness of our systems is shown.

AB - We propose a reconfiguration scheme of repairing faulty processors where processors on each level of a binary tree are considered to be a linear array in which spare processors are inserted at regular intervals. The switching networks for compensation are regular and comparatively simple. The logic circuits are simple and their switchings for repair are done autonomously. We give a method of embedding the proposed tree architectures into two-dimensional arrays for WSI implementations. The method embeds the PE's from the root to a certain level L0 into a rectangular array, which is called a root module. For levels L(>L0), the linear array on each level is partitioned into subarrays. Such subarrays are called level modules. A binary tree-connected computer with a specified height is constructed by embedding these modules into two-dimensional arrays. Next, for the proposed scheme. We derive the necessary and sufficient condition for reconfigurability. Using the result, we obtain a formula for computing system's reliability. The reliabilities of our systems are compared with those of several systems already known, and the effectiveness of our systems is shown.

UR - http://www.scopus.com/inward/record.url?scp=0028201106&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028201106&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0028201106

SN - 0780318501

SP - 132

EP - 142

BT - 1994 IEEE International Conference on Wafer Scale Integration

A2 - Lea, Mike R.

A2 - Tewksbury, Stuart

PB - Publ by IEEE

CY - Piscataway, NJ, United States

ER -