### Abstract

We propose a reconfiguration scheme of repairing faulty processors where processors on each level of a binary tree are considered to be a linear array in which spare processors are inserted at regular intervals. The switching networks for compensation are regular and comparatively simple. The logic circuits are simple and their switchings for repair are done autonomously. We give a method of embedding the proposed tree architectures into two-dimensional arrays for WSI implementations. The method embeds the PE's from the root to a certain level L_{0} into a rectangular array, which is called a root module. For levels L(>L_{0}), the linear array on each level is partitioned into subarrays. Such subarrays are called level modules. A binary tree-connected computer with a specified height is constructed by embedding these modules into two-dimensional arrays. Next, for the proposed scheme. We derive the necessary and sufficient condition for reconfigurability. Using the result, we obtain a formula for computing system's reliability. The reliabilities of our systems are compared with those of several systems already known, and the effectiveness of our systems is shown.

Original language | English |
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Title of host publication | 1994 IEEE International Conference on Wafer Scale Integration |

Editors | Mike R. Lea, Stuart Tewksbury |

Place of Publication | Piscataway, NJ, United States |

Publisher | Publ by IEEE |

Pages | 132-142 |

Number of pages | 11 |

ISBN (Print) | 0780318501 |

Publication status | Published - 1994 |

Externally published | Yes |

Event | Proceedings of the 6th Annual IEEE International Conference on Wafer Scale Integration - San Francisco, CA, USA Duration: 1994 Jan 19 → 1994 Jan 21 |

### Other

Other | Proceedings of the 6th Annual IEEE International Conference on Wafer Scale Integration |
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City | San Francisco, CA, USA |

Period | 94/1/19 → 94/1/21 |

### Fingerprint

### ASJC Scopus subject areas

- Engineering(all)

### Cite this

*1994 IEEE International Conference on Wafer Scale Integration*(pp. 132-142). Piscataway, NJ, United States: Publ by IEEE.

**Reconfigurable fault tolerant binary tree - implementation in two-dimensional arrays and reliability analysis -.** / Takanami, Ituso; Inoue, Katsushi; Watanabe, Takahiro.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

*1994 IEEE International Conference on Wafer Scale Integration.*Publ by IEEE, Piscataway, NJ, United States, pp. 132-142, Proceedings of the 6th Annual IEEE International Conference on Wafer Scale Integration, San Francisco, CA, USA, 94/1/19.

}

TY - GEN

T1 - Reconfigurable fault tolerant binary tree - implementation in two-dimensional arrays and reliability analysis -

AU - Takanami, Ituso

AU - Inoue, Katsushi

AU - Watanabe, Takahiro

PY - 1994

Y1 - 1994

N2 - We propose a reconfiguration scheme of repairing faulty processors where processors on each level of a binary tree are considered to be a linear array in which spare processors are inserted at regular intervals. The switching networks for compensation are regular and comparatively simple. The logic circuits are simple and their switchings for repair are done autonomously. We give a method of embedding the proposed tree architectures into two-dimensional arrays for WSI implementations. The method embeds the PE's from the root to a certain level L0 into a rectangular array, which is called a root module. For levels L(>L0), the linear array on each level is partitioned into subarrays. Such subarrays are called level modules. A binary tree-connected computer with a specified height is constructed by embedding these modules into two-dimensional arrays. Next, for the proposed scheme. We derive the necessary and sufficient condition for reconfigurability. Using the result, we obtain a formula for computing system's reliability. The reliabilities of our systems are compared with those of several systems already known, and the effectiveness of our systems is shown.

AB - We propose a reconfiguration scheme of repairing faulty processors where processors on each level of a binary tree are considered to be a linear array in which spare processors are inserted at regular intervals. The switching networks for compensation are regular and comparatively simple. The logic circuits are simple and their switchings for repair are done autonomously. We give a method of embedding the proposed tree architectures into two-dimensional arrays for WSI implementations. The method embeds the PE's from the root to a certain level L0 into a rectangular array, which is called a root module. For levels L(>L0), the linear array on each level is partitioned into subarrays. Such subarrays are called level modules. A binary tree-connected computer with a specified height is constructed by embedding these modules into two-dimensional arrays. Next, for the proposed scheme. We derive the necessary and sufficient condition for reconfigurability. Using the result, we obtain a formula for computing system's reliability. The reliabilities of our systems are compared with those of several systems already known, and the effectiveness of our systems is shown.

UR - http://www.scopus.com/inward/record.url?scp=0028201106&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028201106&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0028201106

SN - 0780318501

SP - 132

EP - 142

BT - 1994 IEEE International Conference on Wafer Scale Integration

A2 - Lea, Mike R.

A2 - Tewksbury, Stuart

PB - Publ by IEEE

CY - Piscataway, NJ, United States

ER -