Reconfigurable fault tolerant binary tree - implementation in two-dimensional arrays and reliability analysis -

Ituso Takanami, Katsushi Inoue, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

We propose a reconfiguration scheme of repairing faulty processors where processors on each level of a binary tree are considered to be a linear array in which spare processors are inserted at regular intervals. The switching networks for compensation are regular and comparatively simple. The logic circuits are simple and their switchings for repair are done autonomously. We give a method of embedding the proposed tree architectures into two-dimensional arrays for WSI implementations. The method embeds the PE's from the root to a certain level L0 into a rectangular array, which is called a root module. For levels L(>L0), the linear array on each level is partitioned into subarrays. Such subarrays are called level modules. A binary tree-connected computer with a specified height is constructed by embedding these modules into two-dimensional arrays. Next, for the proposed scheme. We derive the necessary and sufficient condition for reconfigurability. Using the result, we obtain a formula for computing system's reliability. The reliabilities of our systems are compared with those of several systems already known, and the effectiveness of our systems is shown.

Original languageEnglish
Title of host publication1994 IEEE International Conference on Wafer Scale Integration
EditorsMike R. Lea, Stuart Tewksbury
PublisherPubl by IEEE
Pages132-142
Number of pages11
ISBN (Print)0780318501
Publication statusPublished - 1994 Jan 1
EventProceedings of the 6th Annual IEEE International Conference on Wafer Scale Integration - San Francisco, CA, USA
Duration: 1994 Jan 191994 Jan 21

Publication series

Name1994 IEEE International Conference on Wafer Scale Integration

Other

OtherProceedings of the 6th Annual IEEE International Conference on Wafer Scale Integration
CitySan Francisco, CA, USA
Period94/1/1994/1/21

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint Dive into the research topics of 'Reconfigurable fault tolerant binary tree - implementation in two-dimensional arrays and reliability analysis -'. Together they form a unique fingerprint.

  • Cite this

    Takanami, I., Inoue, K., & Watanabe, T. (1994). Reconfigurable fault tolerant binary tree - implementation in two-dimensional arrays and reliability analysis -. In M. R. Lea, & S. Tewksbury (Eds.), 1994 IEEE International Conference on Wafer Scale Integration (pp. 132-142). (1994 IEEE International Conference on Wafer Scale Integration). Publ by IEEE.