Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application

Yiqing Huang, Qin Liu, Satoshi Goto, Takeshi Ikenaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In H.264/AVC based integer motion estimation engine, fixed architectures based on full pixel or direct sub-sampling pattern are widely used for HDTV application. However, these architectures suffer from either high complexity or quality loss problems. In this paper, an adaptive sub-sampling based reconfigurable architecture is given out. Firstly, by executing pixel difference analysis, the adaptive sub-sampling scheme which uses three hardware friendly patterns is applied on homogeneous macroblock (MB). Secondly, the related architecture introduces one more pipeline stage to build up configurable partial SAD values so that system performance is enhanced. Thirdly, a two-level pixel data organization scheme is proposed to solve data reuse and hardware utilization problems caused by adaptive algorithm. Moreover, one cross based SAD generation structure is introduced to achieve adaptive output results with less hardware cost. Experimental results show that, the proposed architecture can averagely save 61.71% clock cycles and accomplish twice or four times processing capability for homogeneous MBs. The maximum clock frequency is 208MHz under the TSMC 0.18μm technology in worst case conditions(1.62V, 125°C).

Original languageEnglish
Title of host publicationProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Pages463-468
Number of pages6
DOIs
Publication statusPublished - 2009
Event19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09 - Boston, MA
Duration: 2009 May 102009 May 12

Other

Other19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09
CityBoston, MA
Period09/5/1009/5/12

Fingerprint

High definition television
Pixels
Sampling
Hardware
Clocks
Reconfigurable architectures
Motion estimation
Adaptive algorithms
Pipelines
Engines
Processing
Costs

Keywords

  • H.264
  • Reconfigurable Architecture
  • VLSI

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Huang, Y., Liu, Q., Goto, S., & Ikenaga, T. (2009). Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI (pp. 463-468) https://doi.org/10.1145/1531542.1531648

Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application. / Huang, Yiqing; Liu, Qin; Goto, Satoshi; Ikenaga, Takeshi.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2009. p. 463-468.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Huang, Y, Liu, Q, Goto, S & Ikenaga, T 2009, Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application. in Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. pp. 463-468, 19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09, Boston, MA, 09/5/10. https://doi.org/10.1145/1531542.1531648
Huang Y, Liu Q, Goto S, Ikenaga T. Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2009. p. 463-468 https://doi.org/10.1145/1531542.1531648
Huang, Yiqing ; Liu, Qin ; Goto, Satoshi ; Ikenaga, Takeshi. / Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV application. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2009. pp. 463-468
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