Redundant via allocation for layer partition-based redundant via insertion

Jian Wei Shen, Mei Fang Chiang, Song Chen, Wei Guo, Takeshi Yoshimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The occurrence of via defects increases due to the shrinking size in integrated circuit manufacturing. Redundant via insertion is an effective and recommended method to reduce the yield loss caused by via failures. In this paper, we introduce a redundant via allocation problem for layer partition-based model and solve it using genetic algorithm. The result oflayer partition-based model depends on the partition and processing order of layers. With our redundant via allocation, it can be achieved independent of these factors. In our method, we first construct a graph to represent candidate relations between vias and redundant vias, and conflict relations between redundant vias because of design rule violations. Then the connected components of graph are computed. On each component, we can perform redundant via allocation on the boundaries of any layer partition. Genetic algorithm is used to optimize the allocation strategy. Experiment results show that our method can efficiently improve the redundant via insertion rate.

Original languageEnglish
Title of host publicationASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC
Pages734-737
Number of pages4
DOIs
Publication statusPublished - 2009
Event2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha
Duration: 2009 Oct 202009 Oct 23

Other

Other2009 8th IEEE International Conference on ASIC, ASICON 2009
CityChangsha
Period09/10/2009/10/23

Keywords

  • Design for man ufacturability
  • Double via
  • Redundant via

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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