Redundant via insertion based on conflict removal

Jia Liang, Song Chen, Takeshi Yoshimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The occurrence of via defects increases due to the shrinking size in integrated circuit manufacturing. Double-via insertion is an effective and recommended method for improving chip yield and reliability and reducing the yield loss caused by via failures. In this paper we present a genetic algorithm based method to do the double-via insertion for layouts with grid-less or grid-based routing. Design rule violation between redundant via can be represented by a conflict graph whose vertices are redundant vias and edges represent design rule violations. We propose a genetic algorithm based method exploring the optimal removal of some redundant vias to get a conflict-free redundant via set for double via insertion. To reduce the problem size, we will first merge into one vertex (one redundant via) all the connected components that are cliques of the conflict graph. Experiment results show that the effectiveness of the proposed method.

Original languageEnglish
Title of host publicationICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
Pages794-796
Number of pages3
DOIs
Publication statusPublished - 2010
Event2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - Shanghai
Duration: 2010 Nov 12010 Nov 4

Other

Other2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
CityShanghai
Period10/11/110/11/4

Fingerprint

Genetic algorithms
Integrated circuits
Defects
Experiments

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Liang, J., Chen, S., & Yoshimura, T. (2010). Redundant via insertion based on conflict removal. In ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings (pp. 794-796). [5667425] https://doi.org/10.1109/ICSICT.2010.5667425

Redundant via insertion based on conflict removal. / Liang, Jia; Chen, Song; Yoshimura, Takeshi.

ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2010. p. 794-796 5667425.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Liang, J, Chen, S & Yoshimura, T 2010, Redundant via insertion based on conflict removal. in ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings., 5667425, pp. 794-796, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Shanghai, 10/11/1. https://doi.org/10.1109/ICSICT.2010.5667425
Liang J, Chen S, Yoshimura T. Redundant via insertion based on conflict removal. In ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2010. p. 794-796. 5667425 https://doi.org/10.1109/ICSICT.2010.5667425
Liang, Jia ; Chen, Song ; Yoshimura, Takeshi. / Redundant via insertion based on conflict removal. ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2010. pp. 794-796
@inproceedings{e8b53f3bd1274f5493b47b4226c23678,
title = "Redundant via insertion based on conflict removal",
abstract = "The occurrence of via defects increases due to the shrinking size in integrated circuit manufacturing. Double-via insertion is an effective and recommended method for improving chip yield and reliability and reducing the yield loss caused by via failures. In this paper we present a genetic algorithm based method to do the double-via insertion for layouts with grid-less or grid-based routing. Design rule violation between redundant via can be represented by a conflict graph whose vertices are redundant vias and edges represent design rule violations. We propose a genetic algorithm based method exploring the optimal removal of some redundant vias to get a conflict-free redundant via set for double via insertion. To reduce the problem size, we will first merge into one vertex (one redundant via) all the connected components that are cliques of the conflict graph. Experiment results show that the effectiveness of the proposed method.",
author = "Jia Liang and Song Chen and Takeshi Yoshimura",
year = "2010",
doi = "10.1109/ICSICT.2010.5667425",
language = "English",
isbn = "9781424457984",
pages = "794--796",
booktitle = "ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings",

}

TY - GEN

T1 - Redundant via insertion based on conflict removal

AU - Liang, Jia

AU - Chen, Song

AU - Yoshimura, Takeshi

PY - 2010

Y1 - 2010

N2 - The occurrence of via defects increases due to the shrinking size in integrated circuit manufacturing. Double-via insertion is an effective and recommended method for improving chip yield and reliability and reducing the yield loss caused by via failures. In this paper we present a genetic algorithm based method to do the double-via insertion for layouts with grid-less or grid-based routing. Design rule violation between redundant via can be represented by a conflict graph whose vertices are redundant vias and edges represent design rule violations. We propose a genetic algorithm based method exploring the optimal removal of some redundant vias to get a conflict-free redundant via set for double via insertion. To reduce the problem size, we will first merge into one vertex (one redundant via) all the connected components that are cliques of the conflict graph. Experiment results show that the effectiveness of the proposed method.

AB - The occurrence of via defects increases due to the shrinking size in integrated circuit manufacturing. Double-via insertion is an effective and recommended method for improving chip yield and reliability and reducing the yield loss caused by via failures. In this paper we present a genetic algorithm based method to do the double-via insertion for layouts with grid-less or grid-based routing. Design rule violation between redundant via can be represented by a conflict graph whose vertices are redundant vias and edges represent design rule violations. We propose a genetic algorithm based method exploring the optimal removal of some redundant vias to get a conflict-free redundant via set for double via insertion. To reduce the problem size, we will first merge into one vertex (one redundant via) all the connected components that are cliques of the conflict graph. Experiment results show that the effectiveness of the proposed method.

UR - http://www.scopus.com/inward/record.url?scp=78751488913&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=78751488913&partnerID=8YFLogxK

U2 - 10.1109/ICSICT.2010.5667425

DO - 10.1109/ICSICT.2010.5667425

M3 - Conference contribution

AN - SCOPUS:78751488913

SN - 9781424457984

SP - 794

EP - 796

BT - ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

ER -