Redundant via insertion: Removing design rule conflicts and balancing via density

Song Chen, Jianwei Shen, Wei Guo, Mei Fang Chiang, Takeshi Yoshimura

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

The occurrence of via defects increases due to the shrinking size in integrated circuit manufacturing. Redundant via insertion is an effective and recommended method to reduce the yield loss caused by via failures. In this paper, we introduce the redundant via allocation problem for layer partition-based redundant via insertion methods [1] and solve it using the genetic algorithm. At the same time, we use a convex-cost flow model to equilibrate the via density, which is good for the via density rules. The results of layer partition-based model depend on the partition and processing order of metal layers. Furthermore, even we try all of partitions and processing orders, we might miss the optimal solutions. By introducing the redundant via allocation problem on partitioning boundaries, we can avoid the sub-optimality of the original layer-partition based method. The experimental results show that the proposed method got 12 more redundant vias inserted on average and the via density balance can be greatly improved.

Original languageEnglish
Pages (from-to)2372-2379
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE93-A
Issue number12
DOIs
Publication statusPublished - 2010 Dec

Fingerprint

Design Rules
Balancing
Insertion
Partition
Processing
Integrated circuits
Genetic algorithms
Defects
Metals
Costs
Shrinking
Integrated Circuits
Partitioning
Optimality
Optimal Solution
Manufacturing
Conflict
Genetic Algorithm
Experimental Results
Model

Keywords

  • Design for manufacturability
  • Double via
  • Redundant via
  • Via density

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Signal Processing

Cite this

Redundant via insertion : Removing design rule conflicts and balancing via density. / Chen, Song; Shen, Jianwei; Guo, Wei; Chiang, Mei Fang; Yoshimura, Takeshi.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E93-A, No. 12, 12.2010, p. 2372-2379.

Research output: Contribution to journalArticle

Chen, Song ; Shen, Jianwei ; Guo, Wei ; Chiang, Mei Fang ; Yoshimura, Takeshi. / Redundant via insertion : Removing design rule conflicts and balancing via density. In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2010 ; Vol. E93-A, No. 12. pp. 2372-2379.
@article{1f6bd2417770475bb4d5902c390259f9,
title = "Redundant via insertion: Removing design rule conflicts and balancing via density",
abstract = "The occurrence of via defects increases due to the shrinking size in integrated circuit manufacturing. Redundant via insertion is an effective and recommended method to reduce the yield loss caused by via failures. In this paper, we introduce the redundant via allocation problem for layer partition-based redundant via insertion methods [1] and solve it using the genetic algorithm. At the same time, we use a convex-cost flow model to equilibrate the via density, which is good for the via density rules. The results of layer partition-based model depend on the partition and processing order of metal layers. Furthermore, even we try all of partitions and processing orders, we might miss the optimal solutions. By introducing the redundant via allocation problem on partitioning boundaries, we can avoid the sub-optimality of the original layer-partition based method. The experimental results show that the proposed method got 12 more redundant vias inserted on average and the via density balance can be greatly improved.",
keywords = "Design for manufacturability, Double via, Redundant via, Via density",
author = "Song Chen and Jianwei Shen and Wei Guo and Chiang, {Mei Fang} and Takeshi Yoshimura",
year = "2010",
month = "12",
doi = "10.1587/transfun.E93.A.2372",
language = "English",
volume = "E93-A",
pages = "2372--2379",
journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
issn = "0916-8508",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "12",

}

TY - JOUR

T1 - Redundant via insertion

T2 - Removing design rule conflicts and balancing via density

AU - Chen, Song

AU - Shen, Jianwei

AU - Guo, Wei

AU - Chiang, Mei Fang

AU - Yoshimura, Takeshi

PY - 2010/12

Y1 - 2010/12

N2 - The occurrence of via defects increases due to the shrinking size in integrated circuit manufacturing. Redundant via insertion is an effective and recommended method to reduce the yield loss caused by via failures. In this paper, we introduce the redundant via allocation problem for layer partition-based redundant via insertion methods [1] and solve it using the genetic algorithm. At the same time, we use a convex-cost flow model to equilibrate the via density, which is good for the via density rules. The results of layer partition-based model depend on the partition and processing order of metal layers. Furthermore, even we try all of partitions and processing orders, we might miss the optimal solutions. By introducing the redundant via allocation problem on partitioning boundaries, we can avoid the sub-optimality of the original layer-partition based method. The experimental results show that the proposed method got 12 more redundant vias inserted on average and the via density balance can be greatly improved.

AB - The occurrence of via defects increases due to the shrinking size in integrated circuit manufacturing. Redundant via insertion is an effective and recommended method to reduce the yield loss caused by via failures. In this paper, we introduce the redundant via allocation problem for layer partition-based redundant via insertion methods [1] and solve it using the genetic algorithm. At the same time, we use a convex-cost flow model to equilibrate the via density, which is good for the via density rules. The results of layer partition-based model depend on the partition and processing order of metal layers. Furthermore, even we try all of partitions and processing orders, we might miss the optimal solutions. By introducing the redundant via allocation problem on partitioning boundaries, we can avoid the sub-optimality of the original layer-partition based method. The experimental results show that the proposed method got 12 more redundant vias inserted on average and the via density balance can be greatly improved.

KW - Design for manufacturability

KW - Double via

KW - Redundant via

KW - Via density

UR - http://www.scopus.com/inward/record.url?scp=78649999651&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=78649999651&partnerID=8YFLogxK

U2 - 10.1587/transfun.E93.A.2372

DO - 10.1587/transfun.E93.A.2372

M3 - Article

AN - SCOPUS:78649999651

VL - E93-A

SP - 2372

EP - 2379

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 12

ER -