Abstract
Dynamic power gating applicable to FPGA can reduce the power consumption effectively. In this paper, we propose a sophisticated routing architecture for a region oriented FPGA which supports dynamic power gating. This is the first routing solution of dynamic power gating for coarse-grained FPGA. This paper has 2 main contributions. First, it improves the routing resource graph and routing architecture to support special routing for a region oriented FPGA. Second, some routing channels are made wider to avoid congestion. Experimental result shows that 7.7% routing area can be reduced compared with the symmetric Wilton switch box in the region. Also, our proposed FPGA architecture with sophisticated PR can reduce the power consumption of the system implemented in FPGA.
| Original language | English |
|---|---|
| Pages (from-to) | 2199-2207 |
| Number of pages | 9 |
| Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| Volume | E95-A |
| Issue number | 12 |
| DOIs | |
| Publication status | Published - 2012 Dec |
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Keywords
- FPGA
- Low power
- Routing
- Switch box
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Computer Graphics and Computer-Aided Design
- Applied Mathematics
- Signal Processing
Cite this
Region oriented routing FPGA architecture for dynamic power gating. / Li, Ce; Dong, Yiping; Watanabe, Takahiro.
In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E95-A, No. 12, 12.2012, p. 2199-2207.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Region oriented routing FPGA architecture for dynamic power gating
AU - Li, Ce
AU - Dong, Yiping
AU - Watanabe, Takahiro
PY - 2012/12
Y1 - 2012/12
N2 - Dynamic power gating applicable to FPGA can reduce the power consumption effectively. In this paper, we propose a sophisticated routing architecture for a region oriented FPGA which supports dynamic power gating. This is the first routing solution of dynamic power gating for coarse-grained FPGA. This paper has 2 main contributions. First, it improves the routing resource graph and routing architecture to support special routing for a region oriented FPGA. Second, some routing channels are made wider to avoid congestion. Experimental result shows that 7.7% routing area can be reduced compared with the symmetric Wilton switch box in the region. Also, our proposed FPGA architecture with sophisticated PR can reduce the power consumption of the system implemented in FPGA.
AB - Dynamic power gating applicable to FPGA can reduce the power consumption effectively. In this paper, we propose a sophisticated routing architecture for a region oriented FPGA which supports dynamic power gating. This is the first routing solution of dynamic power gating for coarse-grained FPGA. This paper has 2 main contributions. First, it improves the routing resource graph and routing architecture to support special routing for a region oriented FPGA. Second, some routing channels are made wider to avoid congestion. Experimental result shows that 7.7% routing area can be reduced compared with the symmetric Wilton switch box in the region. Also, our proposed FPGA architecture with sophisticated PR can reduce the power consumption of the system implemented in FPGA.
KW - FPGA
KW - Low power
KW - Routing
KW - Switch box
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UR - http://www.scopus.com/inward/citedby.url?scp=84870557511&partnerID=8YFLogxK
U2 - 10.1587/transfun.E95.A.2199
DO - 10.1587/transfun.E95.A.2199
M3 - Article
VL - E95-A
SP - 2199
EP - 2207
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
SN - 0916-8508
IS - 12
ER -