Region oriented routing FPGA architecture for dynamic power gating

Ce Li, Yiping Dong, Takahiro Watanabe

Research output: Contribution to journalArticle

Abstract

Dynamic power gating applicable to FPGA can reduce the power consumption effectively. In this paper, we propose a sophisticated routing architecture for a region oriented FPGA which supports dynamic power gating. This is the first routing solution of dynamic power gating for coarse-grained FPGA. This paper has 2 main contributions. First, it improves the routing resource graph and routing architecture to support special routing for a region oriented FPGA. Second, some routing channels are made wider to avoid congestion. Experimental result shows that 7.7% routing area can be reduced compared with the symmetric Wilton switch box in the region. Also, our proposed FPGA architecture with sophisticated PR can reduce the power consumption of the system implemented in FPGA.

Original languageEnglish
Pages (from-to)2199-2207
Number of pages9
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE95-A
Issue number12
DOIs
Publication statusPublished - 2012 Dec

Fingerprint

Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Routing
Power Consumption
Electric power utilization
Channel Routing
Congestion
Architecture
Switch
Switches
Resources
Experimental Results
Graph in graph theory

Keywords

  • FPGA
  • Low power
  • Routing
  • Switch box

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Signal Processing

Cite this

Region oriented routing FPGA architecture for dynamic power gating. / Li, Ce; Dong, Yiping; Watanabe, Takahiro.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E95-A, No. 12, 12.2012, p. 2199-2207.

Research output: Contribution to journalArticle

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