Register allocation technique using guarded PDG

Akira Koseki, Hideaki Komatsu, Yoshiaki Fukazawa

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    Register allocation for instruction-level parallel processors involves problems that are not considered in register allocation for scalar processors. First, when the same register is allocated to different variables, anti-dependence is generated, which decreases instruction-level parallelism. Second, spill code should be inserted at a suitable position in its object, where it can be executed in parallel with other instructions. These problems do not exist for scalar processors, so existing register allocators take no account of them. This paper describes a new register allocation algorithm for solving these problems, using a graph structure that represents instructions and dependences between them.

    Original languageEnglish
    Title of host publicationProceedings of the International Conference on Supercomputing
    Place of PublicationNew York, NY, United States
    PublisherACM
    Pages270-277
    Number of pages8
    Publication statusPublished - 1996
    EventProceedings of the 1996 International Conference on Supercomputing - Philadelphia, PA, USA
    Duration: 1996 May 251996 May 28

    Other

    OtherProceedings of the 1996 International Conference on Supercomputing
    CityPhiladelphia, PA, USA
    Period96/5/2596/5/28

    Fingerprint

    Hazardous materials spills

    ASJC Scopus subject areas

    • Computer Science(all)

    Cite this

    Koseki, A., Komatsu, H., & Fukazawa, Y. (1996). Register allocation technique using guarded PDG. In Proceedings of the International Conference on Supercomputing (pp. 270-277). New York, NY, United States: ACM.

    Register allocation technique using guarded PDG. / Koseki, Akira; Komatsu, Hideaki; Fukazawa, Yoshiaki.

    Proceedings of the International Conference on Supercomputing. New York, NY, United States : ACM, 1996. p. 270-277.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Koseki, A, Komatsu, H & Fukazawa, Y 1996, Register allocation technique using guarded PDG. in Proceedings of the International Conference on Supercomputing. ACM, New York, NY, United States, pp. 270-277, Proceedings of the 1996 International Conference on Supercomputing, Philadelphia, PA, USA, 96/5/25.
    Koseki A, Komatsu H, Fukazawa Y. Register allocation technique using guarded PDG. In Proceedings of the International Conference on Supercomputing. New York, NY, United States: ACM. 1996. p. 270-277
    Koseki, Akira ; Komatsu, Hideaki ; Fukazawa, Yoshiaki. / Register allocation technique using guarded PDG. Proceedings of the International Conference on Supercomputing. New York, NY, United States : ACM, 1996. pp. 270-277
    @inproceedings{bed8236e077f48658df12dccd8850043,
    title = "Register allocation technique using guarded PDG",
    abstract = "Register allocation for instruction-level parallel processors involves problems that are not considered in register allocation for scalar processors. First, when the same register is allocated to different variables, anti-dependence is generated, which decreases instruction-level parallelism. Second, spill code should be inserted at a suitable position in its object, where it can be executed in parallel with other instructions. These problems do not exist for scalar processors, so existing register allocators take no account of them. This paper describes a new register allocation algorithm for solving these problems, using a graph structure that represents instructions and dependences between them.",
    author = "Akira Koseki and Hideaki Komatsu and Yoshiaki Fukazawa",
    year = "1996",
    language = "English",
    pages = "270--277",
    booktitle = "Proceedings of the International Conference on Supercomputing",
    publisher = "ACM",

    }

    TY - GEN

    T1 - Register allocation technique using guarded PDG

    AU - Koseki, Akira

    AU - Komatsu, Hideaki

    AU - Fukazawa, Yoshiaki

    PY - 1996

    Y1 - 1996

    N2 - Register allocation for instruction-level parallel processors involves problems that are not considered in register allocation for scalar processors. First, when the same register is allocated to different variables, anti-dependence is generated, which decreases instruction-level parallelism. Second, spill code should be inserted at a suitable position in its object, where it can be executed in parallel with other instructions. These problems do not exist for scalar processors, so existing register allocators take no account of them. This paper describes a new register allocation algorithm for solving these problems, using a graph structure that represents instructions and dependences between them.

    AB - Register allocation for instruction-level parallel processors involves problems that are not considered in register allocation for scalar processors. First, when the same register is allocated to different variables, anti-dependence is generated, which decreases instruction-level parallelism. Second, spill code should be inserted at a suitable position in its object, where it can be executed in parallel with other instructions. These problems do not exist for scalar processors, so existing register allocators take no account of them. This paper describes a new register allocation algorithm for solving these problems, using a graph structure that represents instructions and dependences between them.

    UR - http://www.scopus.com/inward/record.url?scp=0029707465&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=0029707465&partnerID=8YFLogxK

    M3 - Conference contribution

    AN - SCOPUS:0029707465

    SP - 270

    EP - 277

    BT - Proceedings of the International Conference on Supercomputing

    PB - ACM

    CY - New York, NY, United States

    ER -