Register allocation technique using guarded PDG

Akira Koseki, Hideaki Komatsu, Yoshiaki Fukazawa

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    Register allocation for instruction-level parallel processors involves problems that are not considered in register allocation for scalar processors. First, when the same register is allocated to different variables, anti-dependence is generated, which decreases instruction-level parallelism. Second, spill code should be inserted at a suitable position in its object, where it can be executed in parallel with other instructions. These problems do not exist for scalar processors, so existing register allocators take no account of them. This paper describes a new register allocation algorithm for solving these problems, using a graph structure that represents instructions and dependences between them.

    Original languageEnglish
    Title of host publicationProceedings of the International Conference on Supercomputing
    Place of PublicationNew York, NY, United States
    PublisherACM
    Pages270-277
    Number of pages8
    Publication statusPublished - 1996
    EventProceedings of the 1996 International Conference on Supercomputing - Philadelphia, PA, USA
    Duration: 1996 May 251996 May 28

    Other

    OtherProceedings of the 1996 International Conference on Supercomputing
    CityPhiladelphia, PA, USA
    Period96/5/2596/5/28

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    ASJC Scopus subject areas

    • Computer Science(all)

    Cite this

    Koseki, A., Komatsu, H., & Fukazawa, Y. (1996). Register allocation technique using guarded PDG. In Proceedings of the International Conference on Supercomputing (pp. 270-277). ACM.