Register allocation technique using register existence graph

A. Koseki, H. Komastu, Yoshiaki Fukazawa

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    Optimizing compilation is very important for generating code sequences in order to utilize the characteristics of processor architectures. One of the most essential optimization techniques is register allocation. In register allocation that takes account of instruction-level parallelism, anti-dependences generated when the same register is allocated to different variables, and spill code generated when the number of registers is insufficient should be handled in such a way that the parallelism in a program is not lost. In our method, we realized register allocation using a new data structure called the register existence graph, in which the parallelism in a program is well expressed.

    Original languageEnglish
    Title of host publicationProceedings of the International Conference on Parallel Processing
    PublisherIEEE
    Pages404-411
    Number of pages8
    Publication statusPublished - 1997
    EventProceedings of the 1997 International Conference on Parallel Processing - Bloomington, IL, USA
    Duration: 1997 Sep 111997 Sep 15

    Other

    OtherProceedings of the 1997 International Conference on Parallel Processing
    CityBloomington, IL, USA
    Period97/9/1197/9/15

    Fingerprint

    Hazardous materials spills
    Data structures

    ASJC Scopus subject areas

    • Hardware and Architecture

    Cite this

    Koseki, A., Komastu, H., & Fukazawa, Y. (1997). Register allocation technique using register existence graph. In Proceedings of the International Conference on Parallel Processing (pp. 404-411). IEEE.

    Register allocation technique using register existence graph. / Koseki, A.; Komastu, H.; Fukazawa, Yoshiaki.

    Proceedings of the International Conference on Parallel Processing. IEEE, 1997. p. 404-411.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Koseki, A, Komastu, H & Fukazawa, Y 1997, Register allocation technique using register existence graph. in Proceedings of the International Conference on Parallel Processing. IEEE, pp. 404-411, Proceedings of the 1997 International Conference on Parallel Processing, Bloomington, IL, USA, 97/9/11.
    Koseki A, Komastu H, Fukazawa Y. Register allocation technique using register existence graph. In Proceedings of the International Conference on Parallel Processing. IEEE. 1997. p. 404-411
    Koseki, A. ; Komastu, H. ; Fukazawa, Yoshiaki. / Register allocation technique using register existence graph. Proceedings of the International Conference on Parallel Processing. IEEE, 1997. pp. 404-411
    @inproceedings{00006752ca40461aa143b78ac8ea04b3,
    title = "Register allocation technique using register existence graph",
    abstract = "Optimizing compilation is very important for generating code sequences in order to utilize the characteristics of processor architectures. One of the most essential optimization techniques is register allocation. In register allocation that takes account of instruction-level parallelism, anti-dependences generated when the same register is allocated to different variables, and spill code generated when the number of registers is insufficient should be handled in such a way that the parallelism in a program is not lost. In our method, we realized register allocation using a new data structure called the register existence graph, in which the parallelism in a program is well expressed.",
    author = "A. Koseki and H. Komastu and Yoshiaki Fukazawa",
    year = "1997",
    language = "English",
    pages = "404--411",
    booktitle = "Proceedings of the International Conference on Parallel Processing",
    publisher = "IEEE",

    }

    TY - GEN

    T1 - Register allocation technique using register existence graph

    AU - Koseki, A.

    AU - Komastu, H.

    AU - Fukazawa, Yoshiaki

    PY - 1997

    Y1 - 1997

    N2 - Optimizing compilation is very important for generating code sequences in order to utilize the characteristics of processor architectures. One of the most essential optimization techniques is register allocation. In register allocation that takes account of instruction-level parallelism, anti-dependences generated when the same register is allocated to different variables, and spill code generated when the number of registers is insufficient should be handled in such a way that the parallelism in a program is not lost. In our method, we realized register allocation using a new data structure called the register existence graph, in which the parallelism in a program is well expressed.

    AB - Optimizing compilation is very important for generating code sequences in order to utilize the characteristics of processor architectures. One of the most essential optimization techniques is register allocation. In register allocation that takes account of instruction-level parallelism, anti-dependences generated when the same register is allocated to different variables, and spill code generated when the number of registers is insufficient should be handled in such a way that the parallelism in a program is not lost. In our method, we realized register allocation using a new data structure called the register existence graph, in which the parallelism in a program is well expressed.

    UR - http://www.scopus.com/inward/record.url?scp=0030692456&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=0030692456&partnerID=8YFLogxK

    M3 - Conference contribution

    SP - 404

    EP - 411

    BT - Proceedings of the International Conference on Parallel Processing

    PB - IEEE

    ER -