RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE.

Masaki Kumanoya, Kazuyasu Fujishima, Hideshi Miyatake, Yasumasa Nishimura, Kazunori Saito, Takayuki Matsukawa, Tsutomu Yoshihara, Takao Nakano

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

A single 5-V supply 1-Mb DRAM using a half V//c//c biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

Original languageEnglish
JournalIEEE Journal of Solid-State Circuits
VolumeSC-20
Issue number5
Publication statusPublished - 1985 Oct
Externally publishedYes

Fingerprint

Dynamic random access storage
Redundancy
Titanium
Electric fields
Data storage equipment
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Kumanoya, M., Fujishima, K., Miyatake, H., Nishimura, Y., Saito, K., Matsukawa, T., ... Nakano, T. (1985). RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE. IEEE Journal of Solid-State Circuits, SC-20(5).

RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE. / Kumanoya, Masaki; Fujishima, Kazuyasu; Miyatake, Hideshi; Nishimura, Yasumasa; Saito, Kazunori; Matsukawa, Takayuki; Yoshihara, Tsutomu; Nakano, Takao.

In: IEEE Journal of Solid-State Circuits, Vol. SC-20, No. 5, 10.1985.

Research output: Contribution to journalArticle

Kumanoya, M, Fujishima, K, Miyatake, H, Nishimura, Y, Saito, K, Matsukawa, T, Yoshihara, T & Nakano, T 1985, 'RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE.', IEEE Journal of Solid-State Circuits, vol. SC-20, no. 5.
Kumanoya M, Fujishima K, Miyatake H, Nishimura Y, Saito K, Matsukawa T et al. RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE. IEEE Journal of Solid-State Circuits. 1985 Oct;SC-20(5).
Kumanoya, Masaki ; Fujishima, Kazuyasu ; Miyatake, Hideshi ; Nishimura, Yasumasa ; Saito, Kazunori ; Matsukawa, Takayuki ; Yoshihara, Tsutomu ; Nakano, Takao. / RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE. In: IEEE Journal of Solid-State Circuits. 1985 ; Vol. SC-20, No. 5.
@article{8d416991703d4d37917a0c040135bce4,
title = "RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE.",
abstract = "A single 5-V supply 1-Mb DRAM using a half V//c//c biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.",
author = "Masaki Kumanoya and Kazuyasu Fujishima and Hideshi Miyatake and Yasumasa Nishimura and Kazunori Saito and Takayuki Matsukawa and Tsutomu Yoshihara and Takao Nakano",
year = "1985",
month = "10",
language = "English",
volume = "SC-20",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "5",

}

TY - JOUR

T1 - RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE.

AU - Kumanoya, Masaki

AU - Fujishima, Kazuyasu

AU - Miyatake, Hideshi

AU - Nishimura, Yasumasa

AU - Saito, Kazunori

AU - Matsukawa, Takayuki

AU - Yoshihara, Tsutomu

AU - Nakano, Takao

PY - 1985/10

Y1 - 1985/10

N2 - A single 5-V supply 1-Mb DRAM using a half V//c//c biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

AB - A single 5-V supply 1-Mb DRAM using a half V//c//c biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

UR - http://www.scopus.com/inward/record.url?scp=0022140487&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0022140487&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0022140487

VL - SC-20

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 5

ER -