RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE.

Masaki Kumanoya, Kazuyasu Fujishima, Hideshi Miyatake, Yasumasa Nishimura, Kazunori Saito, Takayuki Matsukawa, Tsutomu Yoshihara, Takao Nakano

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

A single 5-V supply 1-Mb DRAM using a half V//c//c biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

Original languageEnglish
JournalIEEE Journal of Solid-State Circuits
VolumeSC-20
Issue number5
Publication statusPublished - 1985 Oct
Externally publishedYes

    Fingerprint

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Kumanoya, M., Fujishima, K., Miyatake, H., Nishimura, Y., Saito, K., Matsukawa, T., Yoshihara, T., & Nakano, T. (1985). RELIABLE 1-MBIT DRAM WITH A MULTI-BIT-TEST MODE. IEEE Journal of Solid-State Circuits, SC-20(5).