Residue BDD and its application to the verification of arithmetic circuits

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

The paper describes a verification method for arithmetic circuits based on residue arithmetic. In the verification, a residue module is attached to the specification and the implementation, and these outputs are compared by constructing BDD's. For the BDD construction without node explosion, we introduce a residue BDD whose width is less than or equal to a modulus. The method is useful for multipliers including C6288.

Original languageEnglish
Title of host publicationProceedings - Design Automation Conference
Editors Anon
PublisherIEEE
Pages542-545
Number of pages4
Publication statusPublished - 1995
Externally publishedYes
EventProceedings of the 32nd Design Automation Conference - San Francisco, CA, USA
Duration: 1995 Jun 121995 Jun 16

Other

OtherProceedings of the 32nd Design Automation Conference
CitySan Francisco, CA, USA
Period95/6/1295/6/16

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

Kimura, S. (1995). Residue BDD and its application to the verification of arithmetic circuits. In Anon (Ed.), Proceedings - Design Automation Conference (pp. 542-545). IEEE.

Residue BDD and its application to the verification of arithmetic circuits. / Kimura, Shinji.

Proceedings - Design Automation Conference. ed. / Anon. IEEE, 1995. p. 542-545.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kimura, S 1995, Residue BDD and its application to the verification of arithmetic circuits. in Anon (ed.), Proceedings - Design Automation Conference. IEEE, pp. 542-545, Proceedings of the 32nd Design Automation Conference, San Francisco, CA, USA, 95/6/12.
Kimura S. Residue BDD and its application to the verification of arithmetic circuits. In Anon, editor, Proceedings - Design Automation Conference. IEEE. 1995. p. 542-545
Kimura, Shinji. / Residue BDD and its application to the verification of arithmetic circuits. Proceedings - Design Automation Conference. editor / Anon. IEEE, 1995. pp. 542-545
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