Resource-aware multi-layer floorplanning for partially reconfigurable FPGAs

Nan Liu, Song Chen, Takeshi Yoshimura

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


Modern field programmable gate arrays (FPGAs) with heterogeneous resources are partially reconfigurable. Existing methods of reconfiguration-aware floorplanning have limitations with regard to homogeneous resources; they solve only a part of the reconfigurable problem. In this paper, first, a precise model for partially reconfigurable FPGAs is formulated, and then, a two-phase floorplanning approach is presented. In the proposed approach, resource distribution is taken into consideration at all times. In the first step, a resource-aware insertion-after-remove perturbation is devised on the basis of the multi-layer sequence pair constraint graphs, and resource-aware slack-based moves (RASBM) are made to satisfy resource requirements. In the second step, a resource-aware fixedoutline floorplanner is used, and RASBM are applied to pack the reconfigurable regions on the FPGAs. Experimental results show that the proposed approach is resource- and reconfiguration-aware, and facilitates stable floorplanning. In addition, it reduces the wire-length by 4-28% in the first step, and by 12% on average in the second step compared to the wirelength in previous approaches.

Original languageEnglish
Pages (from-to)501-510
Number of pages10
JournalIEICE Transactions on Electronics
Issue number4
Publication statusPublished - 2013 Apr


  • Multi-layer floorlanning
  • Reconfigurable
  • Resource-aware

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials


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