Robust AES circuit design for delay variation using suspicious timing error prediction

Yuki Yahagi; Masao Yanagisawa; Nozomu Togawa

doi:10.1109/ISOCC.2017.8368789

Robust AES circuit design for delay variation using suspicious timing error prediction

Yuki Yahagi, Masao Yanagisawa, Nozomu Togawa

School of Fundamental Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper proposes a robust AES (advanced encryption standard) circuit for delay variation. In our proposed AES circuit, suspicious timing error prediction circuits (STEPCs) and their associating gating circuit are incorporated into a normal AES circuit to predict timing errors. STEPCs are inserted between inter-module connections and thus we can monitor almost all of the signal paths between registers and effectively prevent timing errors. The simulation results demonstrate that our AES circuit with STEPCs can be overclocked by up to 1.66X with just 8.05% area overheads.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2017, ISOCC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	101-102
Number of pages	2
ISBN (Electronic)	9781538622858
DOIs	https://doi.org/10.1109/ISOCC.2017.8368789
Publication status	Published - 2018 May 29
Event	14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of Duration: 2017 Nov 5 → 2017 Nov 8

Publication series

Name	Proceedings - International SoC Design Conference 2017, ISOCC 2017

Other

Other	14th International SoC Design Conference, ISOCC 2017
Country/Territory	Korea, Republic of
City	Seoul
Period	17/11/5 → 17/11/8

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ISOCC.2017.8368789

Cite this

Yahagi, Y., Yanagisawa, M., & Togawa, N. (2018). Robust AES circuit design for delay variation using suspicious timing error prediction. In Proceedings - International SoC Design Conference 2017, ISOCC 2017 (pp. 101-102). (Proceedings - International SoC Design Conference 2017, ISOCC 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2017.8368789

Robust AES circuit design for delay variation using suspicious timing error prediction. / Yahagi, Yuki; Yanagisawa, Masao ; Togawa, Nozomu.

Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 101-102 (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yahagi, Y, Yanagisawa, M & Togawa, N 2018, Robust AES circuit design for delay variation using suspicious timing error prediction. in Proceedings - International SoC Design Conference 2017, ISOCC 2017. Proceedings - International SoC Design Conference 2017, ISOCC 2017, Institute of Electrical and Electronics Engineers Inc., pp. 101-102, 14th International SoC Design Conference, ISOCC 2017, Seoul, Korea, Republic of, 17/11/5. https://doi.org/10.1109/ISOCC.2017.8368789

@inproceedings{ab1acf0944ab4e27b2d1cb45390bf481,

title = "Robust AES circuit design for delay variation using suspicious timing error prediction",

abstract = "This paper proposes a robust AES (advanced encryption standard) circuit for delay variation. In our proposed AES circuit, suspicious timing error prediction circuits (STEPCs) and their associating gating circuit are incorporated into a normal AES circuit to predict timing errors. STEPCs are inserted between inter-module connections and thus we can monitor almost all of the signal paths between registers and effectively prevent timing errors. The simulation results demonstrate that our AES circuit with STEPCs can be overclocked by up to 1.66X with just 8.05% area overheads.",

author = "Yuki Yahagi and Masao Yanagisawa and Nozomu Togawa",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 14th International SoC Design Conference, ISOCC 2017 ; Conference date: 05-11-2017 Through 08-11-2017",

year = "2018",

month = may,

day = "29",

doi = "10.1109/ISOCC.2017.8368789",

language = "English",

series = "Proceedings - International SoC Design Conference 2017, ISOCC 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "101--102",

booktitle = "Proceedings - International SoC Design Conference 2017, ISOCC 2017",

}

TY - GEN

T1 - Robust AES circuit design for delay variation using suspicious timing error prediction

AU - Yahagi, Yuki

AU - Yanagisawa, Masao

AU - Togawa, Nozomu

PY - 2018/5/29

Y1 - 2018/5/29

N2 - This paper proposes a robust AES (advanced encryption standard) circuit for delay variation. In our proposed AES circuit, suspicious timing error prediction circuits (STEPCs) and their associating gating circuit are incorporated into a normal AES circuit to predict timing errors. STEPCs are inserted between inter-module connections and thus we can monitor almost all of the signal paths between registers and effectively prevent timing errors. The simulation results demonstrate that our AES circuit with STEPCs can be overclocked by up to 1.66X with just 8.05% area overheads.

AB - This paper proposes a robust AES (advanced encryption standard) circuit for delay variation. In our proposed AES circuit, suspicious timing error prediction circuits (STEPCs) and their associating gating circuit are incorporated into a normal AES circuit to predict timing errors. STEPCs are inserted between inter-module connections and thus we can monitor almost all of the signal paths between registers and effectively prevent timing errors. The simulation results demonstrate that our AES circuit with STEPCs can be overclocked by up to 1.66X with just 8.05% area overheads.

UR - http://www.scopus.com/inward/record.url?scp=85048887213&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85048887213&partnerID=8YFLogxK

U2 - 10.1109/ISOCC.2017.8368789

DO - 10.1109/ISOCC.2017.8368789

M3 - Conference contribution

AN - SCOPUS:85048887213

T3 - Proceedings - International SoC Design Conference 2017, ISOCC 2017

SP - 101

EP - 102

BT - Proceedings - International SoC Design Conference 2017, ISOCC 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 14th International SoC Design Conference, ISOCC 2017

Y2 - 5 November 2017 through 8 November 2017

ER -

Robust AES circuit design for delay variation using suspicious timing error prediction

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