Robust AES circuit design for delay variation using suspicious timing error prediction

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    This paper proposes a robust AES (advanced encryption standard) circuit for delay variation. In our proposed AES circuit, suspicious timing error prediction circuits (STEPCs) and their associating gating circuit are incorporated into a normal AES circuit to predict timing errors. STEPCs are inserted between inter-module connections and thus we can monitor almost all of the signal paths between registers and effectively prevent timing errors. The simulation results demonstrate that our AES circuit with STEPCs can be overclocked by up to 1.66X with just 8.05% area overheads.

    Original languageEnglish
    Title of host publicationProceedings - International SoC Design Conference 2017, ISOCC 2017
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages101-102
    Number of pages2
    ISBN (Electronic)9781538622858
    DOIs
    Publication statusPublished - 2018 May 29
    Event14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of
    Duration: 2017 Nov 52017 Nov 8

    Other

    Other14th International SoC Design Conference, ISOCC 2017
    CountryKorea, Republic of
    CitySeoul
    Period17/11/517/11/8

      Fingerprint

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering
    • Electronic, Optical and Magnetic Materials

    Cite this

    Yahagi, Y., Yanagisawa, M., & Togawa, N. (2018). Robust AES circuit design for delay variation using suspicious timing error prediction. In Proceedings - International SoC Design Conference 2017, ISOCC 2017 (pp. 101-102). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2017.8368789