Robust heuristics for multi-level logic simplification considering local circuit structure

Qiang Zhu, Yusuke Matsunaga, Shinji Kimura, Katsumasa Watanabe

Research output: Contribution to journalArticle

Abstract

Combinational logic circuits are usually implemented as multi-level networks of logic nodes. Multi-level logic simplification using the don't cares on each node is widely used. Large don't cares give good simplification results, but suffer from huge memory area and computation time. Extraction of useful don't cares and reduction of the size of the don't cares are important problems on the simplification using don't cares. In the paper, we propose a new robust heuristic method for the selection of don't cares. We consider an adaptive subnetwork for each simplified node in the network and introduce a stepwise enhancement method of the subnetwork considering the memory area and the network structure. The don't cares extracted from the adaptive subnetworks are called the local don't cares. We have implemented our method for satisfiability don't cares and observability don't cares. We have applied the method on MCNC89 benchmarks, and compared the experimental results with those of the SIS system. The results demonstrate the superiority of our method on the quality of the results and on the size of applicable circuits.

Original languageEnglish
Pages (from-to)2520-2527
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE83-A
Issue number12
Publication statusPublished - 2000 Dec
Externally publishedYes

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Simplification
Heuristics
Logic
Data storage equipment
Combinatorial circuits
Heuristic methods
Networks (circuits)
Logic circuits
Observability
Vertex of a graph
Robust Methods
Heuristic Method
Network Structure
Enhancement
Benchmark
Experimental Results
Demonstrate

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Information Systems

Cite this

Robust heuristics for multi-level logic simplification considering local circuit structure. / Zhu, Qiang; Matsunaga, Yusuke; Kimura, Shinji; Watanabe, Katsumasa.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E83-A, No. 12, 12.2000, p. 2520-2527.

Research output: Contribution to journalArticle

@article{cb75e78e4bc1417799a6420374231b52,
title = "Robust heuristics for multi-level logic simplification considering local circuit structure",
abstract = "Combinational logic circuits are usually implemented as multi-level networks of logic nodes. Multi-level logic simplification using the don't cares on each node is widely used. Large don't cares give good simplification results, but suffer from huge memory area and computation time. Extraction of useful don't cares and reduction of the size of the don't cares are important problems on the simplification using don't cares. In the paper, we propose a new robust heuristic method for the selection of don't cares. We consider an adaptive subnetwork for each simplified node in the network and introduce a stepwise enhancement method of the subnetwork considering the memory area and the network structure. The don't cares extracted from the adaptive subnetworks are called the local don't cares. We have implemented our method for satisfiability don't cares and observability don't cares. We have applied the method on MCNC89 benchmarks, and compared the experimental results with those of the SIS system. The results demonstrate the superiority of our method on the quality of the results and on the size of applicable circuits.",
author = "Qiang Zhu and Yusuke Matsunaga and Shinji Kimura and Katsumasa Watanabe",
year = "2000",
month = "12",
language = "English",
volume = "E83-A",
pages = "2520--2527",
journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
issn = "0916-8508",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "12",

}

TY - JOUR

T1 - Robust heuristics for multi-level logic simplification considering local circuit structure

AU - Zhu, Qiang

AU - Matsunaga, Yusuke

AU - Kimura, Shinji

AU - Watanabe, Katsumasa

PY - 2000/12

Y1 - 2000/12

N2 - Combinational logic circuits are usually implemented as multi-level networks of logic nodes. Multi-level logic simplification using the don't cares on each node is widely used. Large don't cares give good simplification results, but suffer from huge memory area and computation time. Extraction of useful don't cares and reduction of the size of the don't cares are important problems on the simplification using don't cares. In the paper, we propose a new robust heuristic method for the selection of don't cares. We consider an adaptive subnetwork for each simplified node in the network and introduce a stepwise enhancement method of the subnetwork considering the memory area and the network structure. The don't cares extracted from the adaptive subnetworks are called the local don't cares. We have implemented our method for satisfiability don't cares and observability don't cares. We have applied the method on MCNC89 benchmarks, and compared the experimental results with those of the SIS system. The results demonstrate the superiority of our method on the quality of the results and on the size of applicable circuits.

AB - Combinational logic circuits are usually implemented as multi-level networks of logic nodes. Multi-level logic simplification using the don't cares on each node is widely used. Large don't cares give good simplification results, but suffer from huge memory area and computation time. Extraction of useful don't cares and reduction of the size of the don't cares are important problems on the simplification using don't cares. In the paper, we propose a new robust heuristic method for the selection of don't cares. We consider an adaptive subnetwork for each simplified node in the network and introduce a stepwise enhancement method of the subnetwork considering the memory area and the network structure. The don't cares extracted from the adaptive subnetworks are called the local don't cares. We have implemented our method for satisfiability don't cares and observability don't cares. We have applied the method on MCNC89 benchmarks, and compared the experimental results with those of the SIS system. The results demonstrate the superiority of our method on the quality of the results and on the size of applicable circuits.

UR - http://www.scopus.com/inward/record.url?scp=0034511358&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034511358&partnerID=8YFLogxK

M3 - Article

VL - E83-A

SP - 2520

EP - 2527

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 12

ER -