Abstract
Scan technology carries the potential risk of being misused as a side channel to leak out the secrets of crypto cores. The existing scan-based attacks could be viewed as one kind of differential cryptanalysis, which takes advantages of scan chains to observe the bit changes between pairs of chosen plaintexts so as to identify the secret keys. To address such a design/test challenge, this paper proposes a robust secure scan structure design for crypto cores as a countermeasure against scan-based attacks to maintain high security without compromising the testability.
Original language | English |
---|---|
Article number | 5734887 |
Pages (from-to) | 176-181 |
Number of pages | 6 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 20 |
Issue number | 1 |
DOIs | |
Publication status | Published - 2012 Jan |
Keywords
- Crypto hardware
- Differential cryptanalysis
- Scan-based discrete Fourier transform (DFT)
- Security
- Side channel attack
- Testability
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Hardware and Architecture
- Software
Cite this
Robust secure scan design against scan-based differential cryptanalysis. / Shi, Youhua; Togawa, Nozomu; Yanagisawa, Masao; Ohtsuki, Tatsuo.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 1, 5734887, 01.2012, p. 176-181.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Robust secure scan design against scan-based differential cryptanalysis
AU - Shi, Youhua
AU - Togawa, Nozomu
AU - Yanagisawa, Masao
AU - Ohtsuki, Tatsuo
PY - 2012/1
Y1 - 2012/1
N2 - Scan technology carries the potential risk of being misused as a side channel to leak out the secrets of crypto cores. The existing scan-based attacks could be viewed as one kind of differential cryptanalysis, which takes advantages of scan chains to observe the bit changes between pairs of chosen plaintexts so as to identify the secret keys. To address such a design/test challenge, this paper proposes a robust secure scan structure design for crypto cores as a countermeasure against scan-based attacks to maintain high security without compromising the testability.
AB - Scan technology carries the potential risk of being misused as a side channel to leak out the secrets of crypto cores. The existing scan-based attacks could be viewed as one kind of differential cryptanalysis, which takes advantages of scan chains to observe the bit changes between pairs of chosen plaintexts so as to identify the secret keys. To address such a design/test challenge, this paper proposes a robust secure scan structure design for crypto cores as a countermeasure against scan-based attacks to maintain high security without compromising the testability.
KW - Crypto hardware
KW - Differential cryptanalysis
KW - Scan-based discrete Fourier transform (DFT)
KW - Security
KW - Side channel attack
KW - Testability
UR - http://www.scopus.com/inward/record.url?scp=83655190658&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=83655190658&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2011.2120635
DO - 10.1109/TVLSI.2011.2120635
M3 - Article
AN - SCOPUS:83655190658
VL - 20
SP - 176
EP - 181
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 1
M1 - 5734887
ER -