Robust secure scan design against scan-based differential cryptanalysis

Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki

doi:10.1109/TVLSI.2011.2120635

Robust secure scan design against scan-based differential cryptanalysis

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

School of Fundamental Science and Engineering

Research output: Contribution to journal › Article

19 Citations (Scopus)

Abstract

Scan technology carries the potential risk of being misused as a side channel to leak out the secrets of crypto cores. The existing scan-based attacks could be viewed as one kind of differential cryptanalysis, which takes advantages of scan chains to observe the bit changes between pairs of chosen plaintexts so as to identify the secret keys. To address such a design/test challenge, this paper proposes a robust secure scan structure design for crypto cores as a countermeasure against scan-based attacks to maintain high security without compromising the testability.

Original language	English
Article number	5734887
Pages (from-to)	176-181
Number of pages	6
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	20
Issue number	1
DOIs	https://doi.org/10.1109/TVLSI.2011.2120635
Publication status	Published - 2012 Jan 1

Keywords

Crypto hardware
Differential cryptanalysis
Scan-based discrete Fourier transform (DFT)
Security
Side channel attack
Testability

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

Cite this

Shi, Y., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2012). Robust secure scan design against scan-based differential cryptanalysis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(1), 176-181. [5734887]. https://doi.org/10.1109/TVLSI.2011.2120635

@article{f04cadd88f2d45978c1b627c1bf46915,

title = "Robust secure scan design against scan-based differential cryptanalysis",

abstract = "Scan technology carries the potential risk of being misused as a side channel to leak out the secrets of crypto cores. The existing scan-based attacks could be viewed as one kind of differential cryptanalysis, which takes advantages of scan chains to observe the bit changes between pairs of chosen plaintexts so as to identify the secret keys. To address such a design/test challenge, this paper proposes a robust secure scan structure design for crypto cores as a countermeasure against scan-based attacks to maintain high security without compromising the testability.",

keywords = "Crypto hardware, Differential cryptanalysis, Scan-based discrete Fourier transform (DFT), Security, Side channel attack, Testability",

author = "Youhua Shi and Nozomu Togawa and Masao Yanagisawa and Tatsuo Ohtsuki",

year = "2012",

month = jan

day = "1",

doi = "10.1109/TVLSI.2011.2120635",

language = "English",

volume = "20",

pages = "176--181",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

TY - JOUR

T1 - Robust secure scan design against scan-based differential cryptanalysis

AU - Shi, Youhua

AU - Togawa, Nozomu

AU - Yanagisawa, Masao

AU - Ohtsuki, Tatsuo

PY - 2012/1/1

Y1 - 2012/1/1

N2 - Scan technology carries the potential risk of being misused as a side channel to leak out the secrets of crypto cores. The existing scan-based attacks could be viewed as one kind of differential cryptanalysis, which takes advantages of scan chains to observe the bit changes between pairs of chosen plaintexts so as to identify the secret keys. To address such a design/test challenge, this paper proposes a robust secure scan structure design for crypto cores as a countermeasure against scan-based attacks to maintain high security without compromising the testability.

AB - Scan technology carries the potential risk of being misused as a side channel to leak out the secrets of crypto cores. The existing scan-based attacks could be viewed as one kind of differential cryptanalysis, which takes advantages of scan chains to observe the bit changes between pairs of chosen plaintexts so as to identify the secret keys. To address such a design/test challenge, this paper proposes a robust secure scan structure design for crypto cores as a countermeasure against scan-based attacks to maintain high security without compromising the testability.

KW - Crypto hardware

KW - Differential cryptanalysis

KW - Scan-based discrete Fourier transform (DFT)

KW - Security

KW - Side channel attack

KW - Testability

UR - http://www.scopus.com/inward/record.url?scp=83655190658&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=83655190658&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2011.2120635

DO - 10.1109/TVLSI.2011.2120635

M3 - Article

AN - SCOPUS:83655190658

VL - 20

SP - 176

EP - 181

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 1

M1 - 5734887

ER -

Access to Document

10.1109/TVLSI.2011.2120635