Room-temperature ceramic nanocoating using nanosheet deposition technique

M. Osada, T. Sasaki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present a novel procedure for ceramic nanocoating using oxide nanosheet as a building block. A variety of oxide nanosheets (such as Ti 1-δO2, MnO2 and perovsites) were synthesized by delaminating appropriate layered precursors into their molecular single sheets. These nanosheets are exceptionally rich in both structural diversity and electronic properties, with potential applications including conductors, semiconductors, insulators, and ferromagnets. Another attractive aspect is that nanosheets can be organized into various nanoarchitectures by applying solution-based synthetic techniques involving electrostatic layer-by-layer assembly and Langmuir-Blodgett deposition. It is even possible to tailor superlattice assemblies, incorporating into the nanosheet galleries with a wide range of materials such as organic molecules, polymers, and inorganic/metal nanoparticles. Sophisticated functionalities or paper-like devices can be designed through the selection of nanosheets and combining materials, and precise control over their arrangement at the molecular scale.

Original languageEnglish
Title of host publication9th IMAPS/ACerS International Conference and Exhibition on Ceramic Interconnect and Ceramic Microsystems Technologies, CICMT 2013
PublisherIMAPS-International Microelectronics and Packaging Society
Pages14-18
Number of pages5
ISBN (Print)9781629937182
Publication statusPublished - 2013
Externally publishedYes
Event9th IMAPS/ACerS International Conference and Exhibition on Ceramic Interconnect and Ceramic Microsystems Technologies, CICMT 2013 - Orlando, FL, United States
Duration: 2013 Apr 232013 Apr 25

Other

Other9th IMAPS/ACerS International Conference and Exhibition on Ceramic Interconnect and Ceramic Microsystems Technologies, CICMT 2013
CountryUnited States
CityOrlando, FL
Period13/4/2313/4/25

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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