Scalability and operating voltage of gate/N- overlap LDD in sub-half-micron regime

M. Shimizu; M. Inuishi; K. Tsukamoto; Y. Akasaka

Scalability and operating voltage of gate/N^- overlap LDD in sub-half-micron regime

M. Shimizu, M. Inuishi, K. Tsukamoto, Y. Akasaka

Research output: Contribution to journal › Conference article › peer-review

Abstract

The scalability of overlap LDD (OL-LDD) and single drain (SD) CMOSFETs is examined with respect to the allowable operating voltage (V_Dmax) relevant to hot carrier reliability, time-dependent dielectric breakdown (TDDB) reliability, and short channel effects. V_Dmax is almost independent of the gate oxide thickness. This is because the smaller degradation with thinner gate oxide is counter-balanced with a larger I_sub. It is shown that OL-LDD with t_ox = 7 approximately 9 nm can be operated with 3.3 V. It is concluded that the performance of CMOS devices with OL-LDD is superior to that with SD for L_G down to 0.25 μm.

Original language	English
Pages (from-to)	47-48
Number of pages	2
Journal	Digest of Technical Papers - Symposium on VLSI Technology
Publication status	Published - 1991 Dec 1
Externally published	Yes
Event	1991 Symposium on VLSI Technology - Oiso, Jpn Duration: 1991 May 28 → 1991 May 30

ASJC Scopus subject areas

Electrical and Electronic Engineering

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title = "Scalability and operating voltage of gate/N- overlap LDD in sub-half-micron regime",

abstract = "The scalability of overlap LDD (OL-LDD) and single drain (SD) CMOSFETs is examined with respect to the allowable operating voltage (VDmax) relevant to hot carrier reliability, time-dependent dielectric breakdown (TDDB) reliability, and short channel effects. VDmax is almost independent of the gate oxide thickness. This is because the smaller degradation with thinner gate oxide is counter-balanced with a larger Isub. It is shown that OL-LDD with tox = 7 approximately 9 nm can be operated with 3.3 V. It is concluded that the performance of CMOS devices with OL-LDD is superior to that with SD for LG down to 0.25 μm.",

author = "M. Shimizu and M. Inuishi and K. Tsukamoto and Y. Akasaka",

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note = "1991 Symposium on VLSI Technology ; Conference date: 28-05-1991 Through 30-05-1991",

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T1 - Scalability and operating voltage of gate/N- overlap LDD in sub-half-micron regime

AU - Shimizu, M.

AU - Inuishi, M.

AU - Tsukamoto, K.

AU - Akasaka, Y.

PY - 1991/12/1

Y1 - 1991/12/1

N2 - The scalability of overlap LDD (OL-LDD) and single drain (SD) CMOSFETs is examined with respect to the allowable operating voltage (VDmax) relevant to hot carrier reliability, time-dependent dielectric breakdown (TDDB) reliability, and short channel effects. VDmax is almost independent of the gate oxide thickness. This is because the smaller degradation with thinner gate oxide is counter-balanced with a larger Isub. It is shown that OL-LDD with tox = 7 approximately 9 nm can be operated with 3.3 V. It is concluded that the performance of CMOS devices with OL-LDD is superior to that with SD for LG down to 0.25 μm.

AB - The scalability of overlap LDD (OL-LDD) and single drain (SD) CMOSFETs is examined with respect to the allowable operating voltage (VDmax) relevant to hot carrier reliability, time-dependent dielectric breakdown (TDDB) reliability, and short channel effects. VDmax is almost independent of the gate oxide thickness. This is because the smaller degradation with thinner gate oxide is counter-balanced with a larger Isub. It is shown that OL-LDD with tox = 7 approximately 9 nm can be operated with 3.3 V. It is concluded that the performance of CMOS devices with OL-LDD is superior to that with SD for LG down to 0.25 μm.

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JO - Digest of Technical Papers - Symposium on VLSI Technology

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T2 - 1991 Symposium on VLSI Technology

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