Scalability and operating voltage of gate/N- overlap LDD in sub-half-micron regime

M. Shimizu*, M. Inuishi, K. Tsukamoto, Y. Akasaka

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review


The scalability of overlap LDD (OL-LDD) and single drain (SD) CMOSFETs is examined with respect to the allowable operating voltage (VDmax) relevant to hot carrier reliability, time-dependent dielectric breakdown (TDDB) reliability, and short channel effects. VDmax is almost independent of the gate oxide thickness. This is because the smaller degradation with thinner gate oxide is counter-balanced with a larger Isub. It is shown that OL-LDD with tox = 7 approximately 9 nm can be operated with 3.3 V. It is concluded that the performance of CMOS devices with OL-LDD is superior to that with SD for LG down to 0.25 μm.

Original languageEnglish
Pages (from-to)47-48
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
Publication statusPublished - 1991 Dec 1
Externally publishedYes
Event1991 Symposium on VLSI Technology - Oiso, Jpn
Duration: 1991 May 281991 May 30

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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