Scalability of gate/N- overlapped lightly doped drain in deep-submicrometer regime

Masahiro Shimizu, Katsuyoshi Mitsui, Masahide Inuishi, Hideaki Arima, Chihiro Hamaguchi

Research output: Contribution to journalArticle

Abstract

In this paper an experimental study of the scalability of a gate/N- overlapped lightly doped drain (OL-LDD) structure in the deep-submicrometer regime is presented. Devices were optimized for processes with a design rule down to 0.15 μm. The allowable power supply voltage is obtained by investigating the time-dependent dielectric breakdown reliability, the minimum operating voltage, the gate-induced-drain-leakage current, the drain-induced-barrier-lowering effect and the DC hot carrier reliability. It was found that the maximum allowable supply voltage is mainly limited by the DC hot carrier reliability even in the deep-submicrometer range. A higher current-driving ability in the OL-LDD structure is achieved in comparison to that in a single drain (SD) structure when VDmax is applied as a supply voltage. The OL-LDD structure has a smaller CGD in the inversion region as well as in the accumulated region, as compared with the SD structure, especially with smaller LG. Consequently, the performance of complementary metal-oxide-semiconductor (CMOS) devices with the OL-LDD structure is superior to that with the SD structure in the deep-submicrometer regime. It is also confirmed that the OL-LDD structure has a scaling merit even for 0.15 μm CMOS devices.

Original languageEnglish
Pages (from-to)6340-6347
Number of pages8
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume37
Issue number12
Publication statusPublished - 1998 Dec
Externally publishedYes

Fingerprint

Scalability
MOS devices
Hot carriers
Electric potential
electric potential
semiconductor devices
CMOS
direct current
Electric breakdown
power supplies
Leakage currents
high current
leakage
breakdown
inversions
scaling

Keywords

  • Deep-submicrometer
  • Drain engineering
  • Dual gate CMOS
  • Hot carrier reliability
  • MOSFET

ASJC Scopus subject areas

  • Physics and Astronomy (miscellaneous)
  • Engineering(all)

Cite this

Scalability of gate/N- overlapped lightly doped drain in deep-submicrometer regime. / Shimizu, Masahiro; Mitsui, Katsuyoshi; Inuishi, Masahide; Arima, Hideaki; Hamaguchi, Chihiro.

In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Vol. 37, No. 12, 12.1998, p. 6340-6347.

Research output: Contribution to journalArticle

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