Scaling guideline of DRAM memory cells for maintaining the retention time

Shuichi Ueno, Yasuo Inoue, Masahide Inuishi

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

We propose the model of junction leakage current of local cells. Our model can well explain voltage, temperature dependence and distribution of the leakage current. This model indicates that interface state is considered to control the leakage current and retention time. Based on our model, we found that decreasing the trap density and the electric field are effective for decreasing the leakage current. Moreover, a guideline of trap density, storage capacitance and electric field is proposed for designing future DRAMs to maintain the retention time.

Original languageEnglish
Pages (from-to)84-85
Number of pages2
JournalUnknown Journal
Publication statusPublished - 2000
Externally publishedYes

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Dynamic random access storage
Leakage currents
leakage
scaling
Data storage equipment
cells
Electric fields
traps
electric fields
Interface states
temperature distribution
Capacitance
capacitance
temperature dependence
Electric potential
electric potential
Temperature

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Scaling guideline of DRAM memory cells for maintaining the retention time. / Ueno, Shuichi; Inoue, Yasuo; Inuishi, Masahide.

In: Unknown Journal, 2000, p. 84-85.

Research output: Contribution to journalArticle

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