Scaling guideline of DRAM memory cells for maintaining the retention time

Shuichi Ueno*, Yasuo Inoue, Masahide Inuishi

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

9 Citations (Scopus)


We propose the model of junction leakage current of local cells. Our model can well explain voltage, temperature dependence and distribution of the leakage current. This model indicates that interface state is considered to control the leakage current and retention time. Based on our model, we found that decreasing the trap density and the electric field are effective for decreasing the leakage current. Moreover, a guideline of trap density, storage capacitance and electric field is proposed for designing future DRAMs to maintain the retention time.

Original languageEnglish
Pages (from-to)84-85
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
Publication statusPublished - 2000 Jan 1
Externally publishedYes
Event2000 Symposium on VLSI Technology - Honolulu, HI, USA
Duration: 2000 Jun 132000 Jun 15

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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