Abstract
The need for chemical contamination control for future LSI's is investigated by considering device failure mechanisms. The allowable contamination density is calculated by deducing relationships between the contamination density and resultant defect density from experimental results. In the calculations LSI failures are classified into two groups according to the characteristics of failure-producing defects: macrotype and microtype. The former defects are macroscopic and fatal: a single defect causes a failure. A stricter contamination control is required for smaller devices similar to that predicted by conventional yield theory. This is due to increasing chip area. By contrast the latter defects are of atomic size, and a single defect is not fatal: devices fail when the defect density exceeds some threshold value. Transconductance degradation in MOS transistors due to interface traps and the resultant SRAM operation error is proposed as an example. The threshold defect (or contamination) density for the failure could be 1 × 1011 cm-2 in this model. The allowable contamination density abruptly decreases for a minimum pattern size smaller than 0.1 μm. This is due to increasing fluctuations of defect density in component devices. This failure might cause a bottleneck in developing gigabit memories.
| Original language | English |
|---|---|
| Pages (from-to) | 60-67 |
| Number of pages | 8 |
| Journal | IEEE Transactions on Semiconductor Manufacturing |
| Volume | 7 |
| Issue number | 1 |
| DOIs | |
| Publication status | Published - 1994 Feb |
| Externally published | Yes |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Industrial and Manufacturing Engineering
- Electronic, Optical and Magnetic Materials
- Physics and Astronomy (miscellaneous)
- Condensed Matter Physics
Cite this
Scaling law in ULSI contamination control. / Hiraiwa, Atsushi; Itoga, Toshihiko.
In: IEEE Transactions on Semiconductor Manufacturing, Vol. 7, No. 1, 02.1994, p. 60-67.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Scaling law in ULSI contamination control
AU - Hiraiwa, Atsushi
AU - Itoga, Toshihiko
PY - 1994/2
Y1 - 1994/2
N2 - The need for chemical contamination control for future LSI's is investigated by considering device failure mechanisms. The allowable contamination density is calculated by deducing relationships between the contamination density and resultant defect density from experimental results. In the calculations LSI failures are classified into two groups according to the characteristics of failure-producing defects: macrotype and microtype. The former defects are macroscopic and fatal: a single defect causes a failure. A stricter contamination control is required for smaller devices similar to that predicted by conventional yield theory. This is due to increasing chip area. By contrast the latter defects are of atomic size, and a single defect is not fatal: devices fail when the defect density exceeds some threshold value. Transconductance degradation in MOS transistors due to interface traps and the resultant SRAM operation error is proposed as an example. The threshold defect (or contamination) density for the failure could be 1 × 1011 cm-2 in this model. The allowable contamination density abruptly decreases for a minimum pattern size smaller than 0.1 μm. This is due to increasing fluctuations of defect density in component devices. This failure might cause a bottleneck in developing gigabit memories.
AB - The need for chemical contamination control for future LSI's is investigated by considering device failure mechanisms. The allowable contamination density is calculated by deducing relationships between the contamination density and resultant defect density from experimental results. In the calculations LSI failures are classified into two groups according to the characteristics of failure-producing defects: macrotype and microtype. The former defects are macroscopic and fatal: a single defect causes a failure. A stricter contamination control is required for smaller devices similar to that predicted by conventional yield theory. This is due to increasing chip area. By contrast the latter defects are of atomic size, and a single defect is not fatal: devices fail when the defect density exceeds some threshold value. Transconductance degradation in MOS transistors due to interface traps and the resultant SRAM operation error is proposed as an example. The threshold defect (or contamination) density for the failure could be 1 × 1011 cm-2 in this model. The allowable contamination density abruptly decreases for a minimum pattern size smaller than 0.1 μm. This is due to increasing fluctuations of defect density in component devices. This failure might cause a bottleneck in developing gigabit memories.
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U2 - 10.1109/66.286832
DO - 10.1109/66.286832
M3 - Article
VL - 7
SP - 60
EP - 67
JO - IEEE Transactions on Semiconductor Manufacturing
JF - IEEE Transactions on Semiconductor Manufacturing
SN - 0894-6507
IS - 1
ER -