Second-order polynomial expressions for on-chip interconnect capacitance

Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda

    Research output: Contribution to journalArticle

    2 Citations (Scopus)

    Abstract

    Simple closed-form expressions for efficiently calculating on-chip interconnect capacitances are presented. The formulas are expressed with second-order polynomial functions which do not include exponential functions. The runtime of the proposed formulas is about 2-10 times faster than those of existing formulas. The root mean square (RMS) errors of the proposed formulas are within 1.5%, 1.3%, 3.1%, and 4.6% of the results obtained by a field solver for structures with one line above a ground plane, one line between ground planes, three lines above a ground plane, and three lines between ground planes, respectively. The proposed formulas are also superior in accuracy to existing formulas.

    Original languageEnglish
    Pages (from-to)3453-3460
    Number of pages8
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE88-A
    Issue number12
    DOIs
    Publication statusPublished - 2005 Dec

    Fingerprint

    Exponential functions
    Interconnect
    Capacitance
    Mean square error
    Chip
    Polynomials
    Polynomial
    Line
    Polynomial function
    Closed-form
    Roots

    Keywords

    • Capacitance calculation
    • Capacitance extraction
    • Capacitance formula
    • Interconnect capacitance

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems

    Cite this

    Second-order polynomial expressions for on-chip interconnect capacitance. / Kurokawa, Atsushi; Hashimoto, Masanori; Kasebe, Akira; Huang, Zhangcai; Yang, Yun; Inoue, Yasuaki; Inagaki, Ryosuke; Masuda, Hiroo.

    In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E88-A, No. 12, 12.2005, p. 3453-3460.

    Research output: Contribution to journalArticle

    Kurokawa, A, Hashimoto, M, Kasebe, A, Huang, Z, Yang, Y, Inoue, Y, Inagaki, R & Masuda, H 2005, 'Second-order polynomial expressions for on-chip interconnect capacitance', IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. 3453-3460. https://doi.org/10.1093/ietfec/e88-a.12.3453
    Kurokawa, Atsushi ; Hashimoto, Masanori ; Kasebe, Akira ; Huang, Zhangcai ; Yang, Yun ; Inoue, Yasuaki ; Inagaki, Ryosuke ; Masuda, Hiroo. / Second-order polynomial expressions for on-chip interconnect capacitance. In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2005 ; Vol. E88-A, No. 12. pp. 3453-3460.
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    AU - Hashimoto, Masanori

    AU - Kasebe, Akira

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    AU - Yang, Yun

    AU - Inoue, Yasuaki

    AU - Inagaki, Ryosuke

    AU - Masuda, Hiroo

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