Self-limiting laser thermal process for ultra-shallow junction formation of 50-nm gate CMOS

Akio Shima, Hiroshi Ashihara, Toshiyuki Mine, Yasushi Goto, Masatada Horiuchi, Yun Wang, Somit Talwar, Atsushi Hiraiwa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Citations (Scopus)

Abstract

We have developed a novel LTP that dramatically enhances laser exposure window by controlling the heating process in a self-limiting way (SL-LTP). The Vth roll-offs of MOSFETs formed by this method were remarkably improved compared to those by RTA when offset-spacer and halo-implantation processes were not applied. Its effectiveness was also verified in 50-nm gate CMOS devices for the first time by confirming that the drain current increased with laser fluence beyond the conventional exposure limit.

Original languageEnglish
Title of host publicationTechnical Digest - International Electron Devices Meeting
Pages493-496
Number of pages4
Publication statusPublished - 2003
Externally publishedYes
EventIEEE International Electron Devices Meeting - Washington, DC, United States
Duration: 2003 Dec 82003 Dec 10

Other

OtherIEEE International Electron Devices Meeting
CountryUnited States
CityWashington, DC
Period03/12/803/12/10

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Shima, A., Ashihara, H., Mine, T., Goto, Y., Horiuchi, M., Wang, Y., Talwar, S., & Hiraiwa, A. (2003). Self-limiting laser thermal process for ultra-shallow junction formation of 50-nm gate CMOS. In Technical Digest - International Electron Devices Meeting (pp. 493-496)