Simplified 20-μm pitch vertical interconnection process for 3D chip stacking

Katsuyuki Sakuma, Noriyasu Nagai, Mikiko Saito, Jun Mizuno, Shuichi Shoji

Research output: Contribution to journalArticle

22 Citations (Scopus)

Abstract

This paper describes a simplified vertical interconnection process for three-dimensional (3D) chip stacking. The unique feature of this new process is that the conductive filling material in the through-silicon-vias (TSVs), the microbumps, and the interconnection materials are all fabricated in one processing stage. All of the steps can be performed with the same piece of equipment. Prototype chips with 20-μm-pitch vertical interconnections have been demonstrated successfully. By using this technique, 75-μm deep high-aspect-ratio vias can be completely filled without voids using Ni electroplating and uniform 20-μm-pitch microbumps that are 4-μm tall have been fabricated using Sn-Cu electroplating.

Original languageEnglish
Pages (from-to)339-344
Number of pages6
JournalIEEJ Transactions on Electrical and Electronic Engineering
Volume4
Issue number3
DOIs
Publication statusPublished - 2009 May

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Electroplating
Aspect ratio
Silicon
Processing

Keywords

  • 3D integration
  • Electroplating
  • Lead-free solder
  • Microbump
  • Through-silicon-via (TSV)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Simplified 20-μm pitch vertical interconnection process for 3D chip stacking. / Sakuma, Katsuyuki; Nagai, Noriyasu; Saito, Mikiko; Mizuno, Jun; Shoji, Shuichi.

In: IEEJ Transactions on Electrical and Electronic Engineering, Vol. 4, No. 3, 05.2009, p. 339-344.

Research output: Contribution to journalArticle

@article{ee8fa52058f542a8a71e5a50acf95721,
title = "Simplified 20-μm pitch vertical interconnection process for 3D chip stacking",
abstract = "This paper describes a simplified vertical interconnection process for three-dimensional (3D) chip stacking. The unique feature of this new process is that the conductive filling material in the through-silicon-vias (TSVs), the microbumps, and the interconnection materials are all fabricated in one processing stage. All of the steps can be performed with the same piece of equipment. Prototype chips with 20-μm-pitch vertical interconnections have been demonstrated successfully. By using this technique, 75-μm deep high-aspect-ratio vias can be completely filled without voids using Ni electroplating and uniform 20-μm-pitch microbumps that are 4-μm tall have been fabricated using Sn-Cu electroplating.",
keywords = "3D integration, Electroplating, Lead-free solder, Microbump, Through-silicon-via (TSV)",
author = "Katsuyuki Sakuma and Noriyasu Nagai and Mikiko Saito and Jun Mizuno and Shuichi Shoji",
year = "2009",
month = "5",
doi = "10.1002/tee.20415",
language = "English",
volume = "4",
pages = "339--344",
journal = "IEEJ Transactions on Electrical and Electronic Engineering",
issn = "1931-4973",
publisher = "John Wiley and Sons Inc.",
number = "3",

}

TY - JOUR

T1 - Simplified 20-μm pitch vertical interconnection process for 3D chip stacking

AU - Sakuma, Katsuyuki

AU - Nagai, Noriyasu

AU - Saito, Mikiko

AU - Mizuno, Jun

AU - Shoji, Shuichi

PY - 2009/5

Y1 - 2009/5

N2 - This paper describes a simplified vertical interconnection process for three-dimensional (3D) chip stacking. The unique feature of this new process is that the conductive filling material in the through-silicon-vias (TSVs), the microbumps, and the interconnection materials are all fabricated in one processing stage. All of the steps can be performed with the same piece of equipment. Prototype chips with 20-μm-pitch vertical interconnections have been demonstrated successfully. By using this technique, 75-μm deep high-aspect-ratio vias can be completely filled without voids using Ni electroplating and uniform 20-μm-pitch microbumps that are 4-μm tall have been fabricated using Sn-Cu electroplating.

AB - This paper describes a simplified vertical interconnection process for three-dimensional (3D) chip stacking. The unique feature of this new process is that the conductive filling material in the through-silicon-vias (TSVs), the microbumps, and the interconnection materials are all fabricated in one processing stage. All of the steps can be performed with the same piece of equipment. Prototype chips with 20-μm-pitch vertical interconnections have been demonstrated successfully. By using this technique, 75-μm deep high-aspect-ratio vias can be completely filled without voids using Ni electroplating and uniform 20-μm-pitch microbumps that are 4-μm tall have been fabricated using Sn-Cu electroplating.

KW - 3D integration

KW - Electroplating

KW - Lead-free solder

KW - Microbump

KW - Through-silicon-via (TSV)

UR - http://www.scopus.com/inward/record.url?scp=67649255123&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=67649255123&partnerID=8YFLogxK

U2 - 10.1002/tee.20415

DO - 10.1002/tee.20415

M3 - Article

AN - SCOPUS:67649255123

VL - 4

SP - 339

EP - 344

JO - IEEJ Transactions on Electrical and Electronic Engineering

JF - IEEJ Transactions on Electrical and Electronic Engineering

SN - 1931-4973

IS - 3

ER -