Simulated annealing algorithm applied in low power BIST scheme

Chen Hu, Zhe Zhang, Youhua Shi, Jun Yang, Longxing Shi

Research output: Contribution to journalArticle

Abstract

An approach to approximately optimal group test vectors in a certain length of test patterns is proposed to decrease the number of test vectors based on simulated annealing algorithm. By the scheme of reseeding, this approach makes linear feedback shift register (LFSR) generate optimized groups of vectors, so as to reduce the power consumption without any loss of fault coverage. The experiment result shows that more than 70% power consumption can be reduced while keeping the fault coverage invariable. In addition, the test time is greatly shortened with decreased number of test vectors, which is important in real time device.

Original languageEnglish
Pages (from-to)177-180
Number of pages4
JournalDongnan Daxue Xuebao (Ziran Kexue Ban)/Journal of Southeast University (Natural Science Edition)
Volume32
Issue number2
Publication statusPublished - 2002 Mar 1
Externally publishedYes

Fingerprint

Built-in self test
Simulated annealing
Electric power utilization
Shift registers
Feedback
Experiments

Keywords

  • BIST
  • Low-power consumption
  • Stimulated annealing

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Simulated annealing algorithm applied in low power BIST scheme. / Hu, Chen; Zhang, Zhe; Shi, Youhua; Yang, Jun; Shi, Longxing.

In: Dongnan Daxue Xuebao (Ziran Kexue Ban)/Journal of Southeast University (Natural Science Edition), Vol. 32, No. 2, 01.03.2002, p. 177-180.

Research output: Contribution to journalArticle

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