Simultaneous placement and global routing algorithm for FPGAs

Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    An FPGA layout algorithm is presented, which deals with placement and global routing simultaneously by fully exploiting its regular structure. It is based on a simple and fast top-down hierarchical bi-partitioning, with placement and global routes represented by positions of logic-blocks and pseudo-blocks, respectively. Experimental results for several benchmark circuits demonstrates its efficiency and effectiveness.

    Original languageEnglish
    Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
    PublisherIEEE
    Pages483-486
    Number of pages4
    Volume1
    Publication statusPublished - 1994
    EventProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
    Duration: 1994 May 301994 Jun 2

    Other

    OtherProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6)
    CityLondon, England
    Period94/5/3094/6/2

    Fingerprint

    Routing algorithms
    Field programmable gate arrays (FPGA)
    Networks (circuits)

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Electronic, Optical and Magnetic Materials

    Cite this

    Togawa, N., Sato, M., & Ohtsuki, T. (1994). Simultaneous placement and global routing algorithm for FPGAs. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 1, pp. 483-486). IEEE.

    Simultaneous placement and global routing algorithm for FPGAs. / Togawa, Nozomu; Sato, Masao; Ohtsuki, Tatsuo.

    Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 1 IEEE, 1994. p. 483-486.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Togawa, N, Sato, M & Ohtsuki, T 1994, Simultaneous placement and global routing algorithm for FPGAs. in Proceedings - IEEE International Symposium on Circuits and Systems. vol. 1, IEEE, pp. 483-486, Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6), London, England, 94/5/30.
    Togawa N, Sato M, Ohtsuki T. Simultaneous placement and global routing algorithm for FPGAs. In Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 1. IEEE. 1994. p. 483-486
    Togawa, Nozomu ; Sato, Masao ; Ohtsuki, Tatsuo. / Simultaneous placement and global routing algorithm for FPGAs. Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 1 IEEE, 1994. pp. 483-486
    @inproceedings{541b576c297c482cbc3851cff6fe0c89,
    title = "Simultaneous placement and global routing algorithm for FPGAs",
    abstract = "An FPGA layout algorithm is presented, which deals with placement and global routing simultaneously by fully exploiting its regular structure. It is based on a simple and fast top-down hierarchical bi-partitioning, with placement and global routes represented by positions of logic-blocks and pseudo-blocks, respectively. Experimental results for several benchmark circuits demonstrates its efficiency and effectiveness.",
    author = "Nozomu Togawa and Masao Sato and Tatsuo Ohtsuki",
    year = "1994",
    language = "English",
    volume = "1",
    pages = "483--486",
    booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",
    publisher = "IEEE",

    }

    TY - GEN

    T1 - Simultaneous placement and global routing algorithm for FPGAs

    AU - Togawa, Nozomu

    AU - Sato, Masao

    AU - Ohtsuki, Tatsuo

    PY - 1994

    Y1 - 1994

    N2 - An FPGA layout algorithm is presented, which deals with placement and global routing simultaneously by fully exploiting its regular structure. It is based on a simple and fast top-down hierarchical bi-partitioning, with placement and global routes represented by positions of logic-blocks and pseudo-blocks, respectively. Experimental results for several benchmark circuits demonstrates its efficiency and effectiveness.

    AB - An FPGA layout algorithm is presented, which deals with placement and global routing simultaneously by fully exploiting its regular structure. It is based on a simple and fast top-down hierarchical bi-partitioning, with placement and global routes represented by positions of logic-blocks and pseudo-blocks, respectively. Experimental results for several benchmark circuits demonstrates its efficiency and effectiveness.

    UR - http://www.scopus.com/inward/record.url?scp=0028594636&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=0028594636&partnerID=8YFLogxK

    M3 - Conference contribution

    VL - 1

    SP - 483

    EP - 486

    BT - Proceedings - IEEE International Symposium on Circuits and Systems

    PB - IEEE

    ER -