Simultaneous placement and global routing algorithm for FPGAs

Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki

Research output: Contribution to journalConference article

1 Citation (Scopus)

Abstract

An FPGA layout algorithm is presented, which deals with placement and global routing simultaneously by fully exploiting its regular structure. It is based on a simple and fast top-down hierarchical bi-partitioning, with placement and global routes represented by positions of logic-blocks and pseudo-blocks, respectively. Experimental results for several benchmark circuits demonstrates its efficiency and effectiveness.

Original languageEnglish
Pages (from-to)483-486
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume1
Publication statusPublished - 1994 Dec 1
EventProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
Duration: 1994 May 301994 Jun 2

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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