Abstract
An FPGA layout algorithm is presented, which deals with placement and global routing simultaneously by fully exploiting its regular structure. It is based on a simple and fast top-down hierarchical bi-partitioning, with placement and global routes represented by positions of logic-blocks and pseudo-blocks, respectively. Experimental results for several benchmark circuits demonstrates its efficiency and effectiveness.
| Original language | English |
|---|---|
| Pages (from-to) | 483-486 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 1 |
| Publication status | Published - 1994 Dec 1 |
| Event | Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England Duration: 1994 May 30 → 1994 Jun 2 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering