Simultaneous placement and global routing algorithm for FPGAs with power optimization

Nozomu Togawa, Kaoru Ukai, Masao Yanagisawa, Tatsuo Ohtsuki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper proposes a simultaneous placement and global routing algorithm for FPGAs with power optimization. The algorithm is based on hierarchical bipartitioning of layout regions and sets of logic-blocks. When bipartitioning a layout region, pseudo-blocks are introduced to preserve connections if there exist connections between bipartitioned logic-block sets. A global route is represented by a sequence of pseudo-blocks. Since pseudo-blocks and logic-blocks can be dealt with equally, placement and global routing are processed simultaneously. The algorithm gives weights to the nets with high switching probabilities and assigns the blocks connected by weighted nets to the same region. Thus their length is shortened and the power consumption of a whole circuit can be reduced. The experimental results demonstrate the effectiveness and efficiency of the algorithm.

Original languageEnglish
Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems - Proceedings
PublisherIEEE
Pages125-128
Number of pages4
ISBN (Print)0780351460
Publication statusPublished - 1998 Dec 1
EventProceedings of the 1998 IEEE Asia-Pacific Conference on Circuits and Systems - Microelectronics and Integrating Systems (IEEE APCCAS-98) - Chiangmai, Thailand
Duration: 1998 Nov 241998 Nov 27

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems - Proceedings

Other

OtherProceedings of the 1998 IEEE Asia-Pacific Conference on Circuits and Systems - Microelectronics and Integrating Systems (IEEE APCCAS-98)
CityChiangmai, Thailand
Period98/11/2498/11/27

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Togawa, N., Ukai, K., Yanagisawa, M., & Ohtsuki, T. (1998). Simultaneous placement and global routing algorithm for FPGAs with power optimization. In IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings (pp. 125-128). (IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings). IEEE.