Simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs

Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)

    Abstract

    In layout design of transport-processing FPGAs, it is required that not only routing congestion is kept small but also circuits implemented on them operate with higher operation frequency. This paper extends the proposed simultaneous placement and global routing algorithm for transport-processing FPGAs whose objective is to minimize routing congestion and proposes a new algorithm in which the length of each critical signal path (path length) is limited within a specified upper bound imposed on it (path length constraint). The algorithm is based on hierarchical bipartitioning of layout regions and LUT (LookUp Table) sets to be placed. Each bipartitioning procedure consists of three phases: (0) estimation of path lengths, (1) bipartitioning of a set of terminals, and (2) bipartitioning of a set of LUTs. After searching the paths with tighter path length constraints by estimating path lengths in (0), (1) and (2) are executed so that their path lengths are reduced with higher priority and thus path length constraints are not violated. The algorithm has been implemented and applied to transport-processing circuits compared with conventional approaches. The results demonstrate that the algorithm resolves path length constraints for 11 out of 13 circuits, though it increases routing congestion by an average of 20%. After detailed routing, it achieves 100% routing for all the circuits and decreases a circuit delay by an average of 23%.

    Original languageEnglish
    Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
    Place of PublicationPiscataway, NJ, United States
    PublisherIEEE
    Pages569-578
    Number of pages10
    Publication statusPublished - 1997
    EventProceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC - Chiba, Jpn
    Duration: 1997 Jan 281997 Jan 31

    Other

    OtherProceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC
    CityChiba, Jpn
    Period97/1/2897/1/31

    Fingerprint

    Routing algorithms
    Field programmable gate arrays (FPGA)
    Networks (circuits)
    Processing
    Delay circuits
    Table lookup

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Togawa, N., Sato, M., & Ohtsuki, T. (1997). Simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 569-578). Piscataway, NJ, United States: IEEE.

    Simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs. / Togawa, Nozomu; Sato, Masao; Ohtsuki, Tatsuo.

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States : IEEE, 1997. p. 569-578.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Togawa, N, Sato, M & Ohtsuki, T 1997, Simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. IEEE, Piscataway, NJ, United States, pp. 569-578, Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC, Chiba, Jpn, 97/1/28.
    Togawa N, Sato M, Ohtsuki T. Simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States: IEEE. 1997. p. 569-578
    Togawa, Nozomu ; Sato, Masao ; Ohtsuki, Tatsuo. / Simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States : IEEE, 1997. pp. 569-578
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    abstract = "In layout design of transport-processing FPGAs, it is required that not only routing congestion is kept small but also circuits implemented on them operate with higher operation frequency. This paper extends the proposed simultaneous placement and global routing algorithm for transport-processing FPGAs whose objective is to minimize routing congestion and proposes a new algorithm in which the length of each critical signal path (path length) is limited within a specified upper bound imposed on it (path length constraint). The algorithm is based on hierarchical bipartitioning of layout regions and LUT (LookUp Table) sets to be placed. Each bipartitioning procedure consists of three phases: (0) estimation of path lengths, (1) bipartitioning of a set of terminals, and (2) bipartitioning of a set of LUTs. After searching the paths with tighter path length constraints by estimating path lengths in (0), (1) and (2) are executed so that their path lengths are reduced with higher priority and thus path length constraints are not violated. The algorithm has been implemented and applied to transport-processing circuits compared with conventional approaches. The results demonstrate that the algorithm resolves path length constraints for 11 out of 13 circuits, though it increases routing congestion by an average of 20{\%}. After detailed routing, it achieves 100{\%} routing for all the circuits and decreases a circuit delay by an average of 23{\%}.",
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