Abstract
In layout design of transport-processing FPGAs, it is required that not only routing congestion is kept small but also circuits implemented on them operate with higher operation frequency. This paper extends the proposed simultaneous placement and global routing algorithm for transport-processing FPGAs whose objective is to minimize routing congestion and proposes a new algorithm in which the length of each critical signal path (path length) is limited within a specified upper bound imposed on it (path length constraint). The algorithm is based on hierarchical bipartitioning of layout regions and LUT (LookUp Table) sets to be placed. Each bipartitioning procedure consists of three phases: (0) estimation of path lengths, (1) bipartitioning of a set of terminals, and (2) bipartitioning of a set of LUTs. After searching the paths with tighter path length constraints by estimating path lengths in (0), (1) and (2) are executed so that their path lengths are reduced with higher priority and thus path length constraints are not violated. The algorithm has been implemented and applied to transport-processing circuits compared with conventional approaches. The results demonstrate that the algorithm resolves path length constraints for 11 out of 13 circuits, though it increases routing congestion by an average of 20%. After detailed routing, it achieves 100% routing for all the circuits and decreases a circuit delay by an average of 23%.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC |
| Place of Publication | Piscataway, NJ, United States |
| Publisher | IEEE |
| Pages | 569-578 |
| Number of pages | 10 |
| Publication status | Published - 1997 |
| Event | Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC - Chiba, Jpn Duration: 1997 Jan 28 → 1997 Jan 31 |
Other
| Other | Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC |
|---|---|
| City | Chiba, Jpn |
| Period | 97/1/28 → 97/1/31 |
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ASJC Scopus subject areas
- Engineering(all)
Cite this
Simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs. / Togawa, Nozomu; Sato, Masao; Ohtsuki, Tatsuo.
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States : IEEE, 1997. p. 569-578.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs
AU - Togawa, Nozomu
AU - Sato, Masao
AU - Ohtsuki, Tatsuo
PY - 1997
Y1 - 1997
N2 - In layout design of transport-processing FPGAs, it is required that not only routing congestion is kept small but also circuits implemented on them operate with higher operation frequency. This paper extends the proposed simultaneous placement and global routing algorithm for transport-processing FPGAs whose objective is to minimize routing congestion and proposes a new algorithm in which the length of each critical signal path (path length) is limited within a specified upper bound imposed on it (path length constraint). The algorithm is based on hierarchical bipartitioning of layout regions and LUT (LookUp Table) sets to be placed. Each bipartitioning procedure consists of three phases: (0) estimation of path lengths, (1) bipartitioning of a set of terminals, and (2) bipartitioning of a set of LUTs. After searching the paths with tighter path length constraints by estimating path lengths in (0), (1) and (2) are executed so that their path lengths are reduced with higher priority and thus path length constraints are not violated. The algorithm has been implemented and applied to transport-processing circuits compared with conventional approaches. The results demonstrate that the algorithm resolves path length constraints for 11 out of 13 circuits, though it increases routing congestion by an average of 20%. After detailed routing, it achieves 100% routing for all the circuits and decreases a circuit delay by an average of 23%.
AB - In layout design of transport-processing FPGAs, it is required that not only routing congestion is kept small but also circuits implemented on them operate with higher operation frequency. This paper extends the proposed simultaneous placement and global routing algorithm for transport-processing FPGAs whose objective is to minimize routing congestion and proposes a new algorithm in which the length of each critical signal path (path length) is limited within a specified upper bound imposed on it (path length constraint). The algorithm is based on hierarchical bipartitioning of layout regions and LUT (LookUp Table) sets to be placed. Each bipartitioning procedure consists of three phases: (0) estimation of path lengths, (1) bipartitioning of a set of terminals, and (2) bipartitioning of a set of LUTs. After searching the paths with tighter path length constraints by estimating path lengths in (0), (1) and (2) are executed so that their path lengths are reduced with higher priority and thus path length constraints are not violated. The algorithm has been implemented and applied to transport-processing circuits compared with conventional approaches. The results demonstrate that the algorithm resolves path length constraints for 11 out of 13 circuits, though it increases routing congestion by an average of 20%. After detailed routing, it achieves 100% routing for all the circuits and decreases a circuit delay by an average of 23%.
UR - http://www.scopus.com/inward/record.url?scp=0030712708&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0030712708&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0030712708
SP - 569
EP - 578
BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
PB - IEEE
CY - Piscataway, NJ, United States
ER -