Simultaneous placement and global routing for transport-processing FPGA layout

Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki

    Research output: Contribution to journalArticle

    3 Citations (Scopus)

    Abstract

    Transport-processing FPGAs have been proposed for flexible telecommunication systems. Since those FPGAs have finer granularity of logic functions to implement circuits on them, the amount of routing resources tends to increase. In order to keep routing congestion small, it is necessary to execute placement and routing simultaneously. This paper proposes a simultaneous placement and global routing algorithm for transport-processing FPGAs whose primary objective is minimizing routing congestion. The algorithm is based on hierarchical bipartition of layout regions and sets of LUTs (LookUp Tables) to be placed. It achieves bipartitioning which leads to small routing congestion by applying a network flow technique to it and computing a maximum flow and a minimum cut. If there exist connections between bipartitioned LUT sets, pairs of pseudo-terminals are introduced to preserve the connections. A sequence of pseudo-terminals represents a global route of each net. As a result, both placement of LUTs and global routing are determined when hierarchical bipartitioning procedures are finished. The proposed algorithm has been implemented and applied to practical transport-processing circuits. The experimental results demonstrate that it decreases routing congestion by an average of 37% compared with a conventional algorithm and achieves 100% routing for the circuits for which the conventional algorithm causes unrouted nets.

    Original languageEnglish
    Pages (from-to)2140-2149
    Number of pages10
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE79-A
    Issue number12
    Publication statusPublished - 1996

    Fingerprint

    Field Programmable Gate Array
    Placement
    Table lookup
    Field programmable gate arrays (FPGA)
    Layout
    Routing
    Processing
    Congestion
    Networks (circuits)
    Look-up Table
    Telecommunication systems
    Routing algorithms
    Minimum Cut
    Maximum Flow
    Network Flow
    Routing Algorithm
    Granularity
    Telecommunications
    Tend
    Logic

    Keywords

    • FPGA
    • Layout design
    • Network flow
    • Placement and routing
    • Transport processing

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems

    Cite this

    Simultaneous placement and global routing for transport-processing FPGA layout. / Togawa, Nozomu; Sato, Masao; Ohtsuki, Tatsuo.

    In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E79-A, No. 12, 1996, p. 2140-2149.

    Research output: Contribution to journalArticle

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