Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis

Cong Hao, Jian Mo Ni, Hui Tong Wang, Takeshi Yoshimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper proposes a simultaneous scheduling and binding approach for resource and interconnect reduction in high-level synthesis. The scheme incorporates the operation scheduling into functional unit (FU) and register binding, targeting the reduction of both resource and interconnect reduction. A simplified weighted and ordered compatibility graph (SWOCG) based binding algorithm is also proposed and runs tens of times faster than the WOCG based binding algorithm. The experimental results show that our proposal achieves 4% to 15% reduction in resource usage and interconnect reduction, and also runs 5X faster compared to previous works.

Original languageEnglish
Title of host publicationProceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479984831
DOIs
Publication statusPublished - 2016 Jul 19
Event11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China
Duration: 2015 Nov 32015 Nov 6

Other

Other11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
CountryChina
CityChengdu
Period15/11/315/11/6

Fingerprint

Scheduling
High level synthesis

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Hao, C., Ni, J. M., Wang, H. T., & Yoshimura, T. (2016). Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis. In Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015 [7516908] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASICON.2015.7516908

Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis. / Hao, Cong; Ni, Jian Mo; Wang, Hui Tong; Yoshimura, Takeshi.

Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 2016. 7516908.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hao, C, Ni, JM, Wang, HT & Yoshimura, T 2016, Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis. in Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015., 7516908, Institute of Electrical and Electronics Engineers Inc., 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015, Chengdu, China, 15/11/3. https://doi.org/10.1109/ASICON.2015.7516908
Hao C, Ni JM, Wang HT, Yoshimura T. Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis. In Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc. 2016. 7516908 https://doi.org/10.1109/ASICON.2015.7516908
Hao, Cong ; Ni, Jian Mo ; Wang, Hui Tong ; Yoshimura, Takeshi. / Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis. Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 2016.
@inproceedings{4735ecaf133c4e869315f5de8d6c700f,
title = "Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis",
abstract = "This paper proposes a simultaneous scheduling and binding approach for resource and interconnect reduction in high-level synthesis. The scheme incorporates the operation scheduling into functional unit (FU) and register binding, targeting the reduction of both resource and interconnect reduction. A simplified weighted and ordered compatibility graph (SWOCG) based binding algorithm is also proposed and runs tens of times faster than the WOCG based binding algorithm. The experimental results show that our proposal achieves 4{\%} to 15{\%} reduction in resource usage and interconnect reduction, and also runs 5X faster compared to previous works.",
author = "Cong Hao and Ni, {Jian Mo} and Wang, {Hui Tong} and Takeshi Yoshimura",
year = "2016",
month = "7",
day = "19",
doi = "10.1109/ASICON.2015.7516908",
language = "English",
booktitle = "Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",

}

TY - GEN

T1 - Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis

AU - Hao, Cong

AU - Ni, Jian Mo

AU - Wang, Hui Tong

AU - Yoshimura, Takeshi

PY - 2016/7/19

Y1 - 2016/7/19

N2 - This paper proposes a simultaneous scheduling and binding approach for resource and interconnect reduction in high-level synthesis. The scheme incorporates the operation scheduling into functional unit (FU) and register binding, targeting the reduction of both resource and interconnect reduction. A simplified weighted and ordered compatibility graph (SWOCG) based binding algorithm is also proposed and runs tens of times faster than the WOCG based binding algorithm. The experimental results show that our proposal achieves 4% to 15% reduction in resource usage and interconnect reduction, and also runs 5X faster compared to previous works.

AB - This paper proposes a simultaneous scheduling and binding approach for resource and interconnect reduction in high-level synthesis. The scheme incorporates the operation scheduling into functional unit (FU) and register binding, targeting the reduction of both resource and interconnect reduction. A simplified weighted and ordered compatibility graph (SWOCG) based binding algorithm is also proposed and runs tens of times faster than the WOCG based binding algorithm. The experimental results show that our proposal achieves 4% to 15% reduction in resource usage and interconnect reduction, and also runs 5X faster compared to previous works.

UR - http://www.scopus.com/inward/record.url?scp=84982263921&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84982263921&partnerID=8YFLogxK

U2 - 10.1109/ASICON.2015.7516908

DO - 10.1109/ASICON.2015.7516908

M3 - Conference contribution

BT - Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015

PB - Institute of Electrical and Electronics Engineers Inc.

ER -