Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis

Cong Hao; Jian Mo Ni; Hui Tong Wang; Takeshi Yoshimura

doi:10.1109/ASICON.2015.7516908

Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis

Cong Hao, Jian Mo Ni, Hui Tong Wang, Takeshi Yoshimura

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

This paper proposes a simultaneous scheduling and binding approach for resource and interconnect reduction in high-level synthesis. The scheme incorporates the operation scheduling into functional unit (FU) and register binding, targeting the reduction of both resource and interconnect reduction. A simplified weighted and ordered compatibility graph (SWOCG) based binding algorithm is also proposed and runs tens of times faster than the WOCG based binding algorithm. The experimental results show that our proposal achieves 4% to 15% reduction in resource usage and interconnect reduction, and also runs 5X faster compared to previous works.

Original language	English
Title of host publication	Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479984831
DOIs	https://doi.org/10.1109/ASICON.2015.7516908
Publication status	Published - 2016 Jul 19
Event	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China Duration: 2015 Nov 3 → 2015 Nov 6

Other

Other	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
Country/Territory	China
City	Chengdu
Period	15/11/3 → 15/11/6

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ASICON.2015.7516908

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Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis. / Hao, Cong; Ni, Jian Mo; Wang, Hui Tong et al.

Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 2016. 7516908.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hao, C, Ni, JM, Wang, HT & Yoshimura, T 2016, Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis. in Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015., 7516908, Institute of Electrical and Electronics Engineers Inc., 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015, Chengdu, China, 15/11/3. https://doi.org/10.1109/ASICON.2015.7516908

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title = "Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis",

abstract = "This paper proposes a simultaneous scheduling and binding approach for resource and interconnect reduction in high-level synthesis. The scheme incorporates the operation scheduling into functional unit (FU) and register binding, targeting the reduction of both resource and interconnect reduction. A simplified weighted and ordered compatibility graph (SWOCG) based binding algorithm is also proposed and runs tens of times faster than the WOCG based binding algorithm. The experimental results show that our proposal achieves 4% to 15% reduction in resource usage and interconnect reduction, and also runs 5X faster compared to previous works.",

author = "Cong Hao and Ni, {Jian Mo} and Wang, {Hui Tong} and Takeshi Yoshimura",

year = "2016",

month = jul,

day = "19",

doi = "10.1109/ASICON.2015.7516908",

language = "English",

booktitle = "Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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note = "11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 ; Conference date: 03-11-2015 Through 06-11-2015",

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T1 - Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis

AU - Hao, Cong

AU - Ni, Jian Mo

AU - Wang, Hui Tong

AU - Yoshimura, Takeshi

PY - 2016/7/19

Y1 - 2016/7/19

N2 - This paper proposes a simultaneous scheduling and binding approach for resource and interconnect reduction in high-level synthesis. The scheme incorporates the operation scheduling into functional unit (FU) and register binding, targeting the reduction of both resource and interconnect reduction. A simplified weighted and ordered compatibility graph (SWOCG) based binding algorithm is also proposed and runs tens of times faster than the WOCG based binding algorithm. The experimental results show that our proposal achieves 4% to 15% reduction in resource usage and interconnect reduction, and also runs 5X faster compared to previous works.

AB - This paper proposes a simultaneous scheduling and binding approach for resource and interconnect reduction in high-level synthesis. The scheme incorporates the operation scheduling into functional unit (FU) and register binding, targeting the reduction of both resource and interconnect reduction. A simplified weighted and ordered compatibility graph (SWOCG) based binding algorithm is also proposed and runs tens of times faster than the WOCG based binding algorithm. The experimental results show that our proposal achieves 4% to 15% reduction in resource usage and interconnect reduction, and also runs 5X faster compared to previous works.

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DO - 10.1109/ASICON.2015.7516908

M3 - Conference contribution

AN - SCOPUS:84982263921

BT - Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015

Y2 - 3 November 2015 through 6 November 2015

ER -

Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis

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