Single-chip multiprocessor for smart terminals

Masato Edahiro, Satoshi Matsushita, Masakazu Yamashina, Naoki Nishi

Research output: Contribution to journalArticle

20 Citations (Scopus)

Abstract

The MP98 low-power, high-performance microprocessor architecture has been described. It supports smart information terminals using single-chip multiprocessor technologies. Its first prototype (code named Merlot) achieved 1 giga instructions/sec at 1 watt. Several basic algorithms such as hashing, sorting, and searching were realized in artificial intelligence on the multithreaded architecture. The multiple control flow execution (MCFE) in MP98 helps compilers extract parallelism from software. Performance estimates for speech recognition application has been presented.

Original languageEnglish
Pages (from-to)12-20
Number of pages9
JournalIEEE Micro
Volume20
Issue number4
DOIs
Publication statusPublished - 2000 Jul
Externally publishedYes

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Edahiro, M., Matsushita, S., Yamashina, M., & Nishi, N. (2000). Single-chip multiprocessor for smart terminals. IEEE Micro, 20(4), 12-20. https://doi.org/10.1109/MM.2000.865862