Single chip VLSI chrominance/luminance separator based on a silicon compiler

T. Miyazaki, T. Nishitani, S. Aikoh, M. Ishikawa, Takeshi Yoshimura, K. Mitsuhashi, M. Furuichi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The authors present a single-chip VLSI chrominance/luminance (Y/C) separator that is economically fabricated for NTSC TV signals at 13.5-MHz CCIR standard sampling rate. In order to realize compactness and low power dissipation, two FIR filter architectures and a multiplier structure are proposed. A silicon compiler, which uses these structures, also contributes to fast and error-free VLSI development. The Y/C separator chip has 10.4-mm × 11.7-mm die size and attains about 860-MOPS operating speed.

Original languageEnglish
Title of host publicationICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Editors Anon
PublisherPubl by IEEE
Pages2433-2436
Number of pages4
Volume4
Publication statusPublished - 1989
Externally publishedYes
Event1989 International Conference on Acoustics, Speech, and Signal Processing - Glasgow, Scotland
Duration: 1989 May 231989 May 26

Other

Other1989 International Conference on Acoustics, Speech, and Signal Processing
CityGlasgow, Scotland
Period89/5/2389/5/26

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ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering
  • Acoustics and Ultrasonics

Cite this

Miyazaki, T., Nishitani, T., Aikoh, S., Ishikawa, M., Yoshimura, T., Mitsuhashi, K., & Furuichi, M. (1989). Single chip VLSI chrominance/luminance separator based on a silicon compiler. In Anon (Ed.), ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings (Vol. 4, pp. 2433-2436). Publ by IEEE.