Skew-tolerant global synchronization based on periodically all-in-phase clocking for multi-core SOC platforms

Atsufumi Shibayama, Koichi Nose, Sunao Torii, Masayuki Mizuno, Masato Edahiro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

A periodically all-in-phase clock generator and a skew-tolerant bus wrapper have been developed for multi-core SOC platforms. The clock generator produces clock frequencies in 81-steps, and the bus wrapper makes possible deterministic data transfer among different frequency clocks even when inter-clock skew is as high as 2 clock cycle times. A combination of the clock generator, the bus wrapper, arid loosely balanced global clock distribution serves to case chip-timing design while maintaining deterministic chip behavior.

Original languageEnglish
Title of host publication2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages158-159
Number of pages2
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event2007 Symposium on VLSI Circuits, VLSIC - Kyoto, Japan
Duration: 2007 Jun 142007 Jun 16

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2007 Symposium on VLSI Circuits, VLSIC
CountryJapan
CityKyoto
Period07/6/1407/6/16

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Shibayama, A., Nose, K., Torii, S., Mizuno, M., & Edahiro, M. (2007). Skew-tolerant global synchronization based on periodically all-in-phase clocking for multi-core SOC platforms. In 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers (pp. 158-159). [4342697] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2007.4342697