Small-Area and Low-Power FPGA-Based Multipliers using Approximate Elementary Modules

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Approximate multiplier design is an effective technique to improve hardware performance at the cost of accuracy loss. The current approximate multipliers are mostly ASIC-based and are dedicated for one particular application. In contrast, FPGA has been an attractive choice for many applications, because of its high performance, reconfigurability, and fast development. This paper presents a novel methodology for designing approximate multipliers by employing the FPGA-based fabrics. The area and latency are significantly reduced by cutting the carry propagation path in the multiplier. Moreover, we explore higher-order multipliers on architectural space by using our proposed small-size approximate multipliers as elementary modules. For different accuracy requirements, eight configurations for approximate 8 × 8 multiplier are discussed. In terms of mean relative error distance (MRED), the accuracy loss of the proposed 8 × 8 multiplier is low as 0.17%. Compared with the exact multiplier, our proposed design can reduce area by 43.66% and power by 20.36%. The critical path latency reduction is up to 27.66%. The proposed multiplier design has a better accuracy-hardware tradeoff than other designs with com-parable accuracy.

Original languageEnglish
Title of host publicationASP-DAC 2020 - 25th Asia and South Pacific Design Automation Conference, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages599-604
Number of pages6
ISBN (Electronic)9781728141237
DOIs
Publication statusPublished - 2020 Jan
Event25th Asia and South Pacific Design Automation Conference, ASP-DAC 2020 - Beijing, China
Duration: 2020 Jan 132020 Jan 16

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2020-January

Conference

Conference25th Asia and South Pacific Design Automation Conference, ASP-DAC 2020
CountryChina
CityBeijing
Period20/1/1320/1/16

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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    Guo, Y., Sun, H., & Kimura, S. (2020). Small-Area and Low-Power FPGA-Based Multipliers using Approximate Elementary Modules. In ASP-DAC 2020 - 25th Asia and South Pacific Design Automation Conference, Proceedings (pp. 599-604). [9045546] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2020-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASP-DAC47756.2020.9045546