Small delay fault model for intra-gate resistive open defects

Masayuki Arai*, Akifumi Suto, Katsuyuki Nakano, Michihiro Shintani, Kazuhiko Iwasaki, Kazumi Hatayama, Takashi Aikyo

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

We propose the fault model considering weak resistive opens inside the gate which might cause pattern-sequence-dependent and timing-dependent malfunction of the circuit. We assume the fixed observation interval for the signal transition, and derive the minimum resistance of intra-gate resistive opens to be detected as a fault by SPICE simulation. Based on the simulation results, we establish three fault models, that is, the one considering the location of the resistance, the one considering both the location and the resistance distribution, and the simplified one where str and stf faults considering the signal transition of the input ports are assumed. The coverage calculation for the primitive gates and small benchmark circuit reveals that the proposed models have more accuracy on the detection of weak open defects.

Original languageEnglish
Title of host publicationProceedings - 2009 27th IEEE VLSI Test Symposium, VTS 2009
Pages27-32
Number of pages6
DOIs
Publication statusPublished - 2009
Externally publishedYes
Event2009 27th IEEE VLSI Test Symposium, VTS 2009 - Santa Cruz, CA, United States
Duration: 2009 May 32009 May 7

Publication series

NameProceedings of the IEEE VLSI Test Symposium

Conference

Conference2009 27th IEEE VLSI Test Symposium, VTS 2009
Country/TerritoryUnited States
CitySanta Cruz, CA
Period09/5/309/5/7

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'Small delay fault model for intra-gate resistive open defects'. Together they form a unique fingerprint.

Cite this