Small delay fault model for intra-gate resistive open defects

Masayuki Arai; Akifumi Suto; Katsuyuki Nakano; Michihiro Shintani; Kazuhiko Iwasaki; Kazumi Hatayama; Takashi Aikyo

doi:10.1109/VTS.2009.25

Small delay fault model for intra-gate resistive open defects

Masayuki Arai^*, Akifumi Suto, Katsuyuki Nakano, Michihiro Shintani, Kazuhiko Iwasaki, Kazumi Hatayama, Takashi Aikyo

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Citations (Scopus)

Abstract

We propose the fault model considering weak resistive opens inside the gate which might cause pattern-sequence-dependent and timing-dependent malfunction of the circuit. We assume the fixed observation interval for the signal transition, and derive the minimum resistance of intra-gate resistive opens to be detected as a fault by SPICE simulation. Based on the simulation results, we establish three fault models, that is, the one considering the location of the resistance, the one considering both the location and the resistance distribution, and the simplified one where str and stf faults considering the signal transition of the input ports are assumed. The coverage calculation for the primitive gates and small benchmark circuit reveals that the proposed models have more accuracy on the detection of weak open defects.

Original language	English
Title of host publication	Proceedings - 2009 27th IEEE VLSI Test Symposium, VTS 2009
Pages	27-32
Number of pages	6
DOIs	https://doi.org/10.1109/VTS.2009.25
Publication status	Published - 2009
Externally published	Yes
Event	2009 27th IEEE VLSI Test Symposium, VTS 2009 - Santa Cruz, CA, United States Duration: 2009 May 3 → 2009 May 7

Publication series

Name	Proceedings of the IEEE VLSI Test Symposium

Conference

Conference	2009 27th IEEE VLSI Test Symposium, VTS 2009
Country/Territory	United States
City	Santa Cruz, CA
Period	09/5/3 → 09/5/7

ASJC Scopus subject areas

Computer Science Applications
Electrical and Electronic Engineering

Access to Document

10.1109/VTS.2009.25

Cite this

Arai, M, Suto, A, Nakano, K, Shintani, M, Iwasaki, K, Hatayama, K & Aikyo, T 2009, Small delay fault model for intra-gate resistive open defects. in Proceedings - 2009 27th IEEE VLSI Test Symposium, VTS 2009., 5116605, Proceedings of the IEEE VLSI Test Symposium, pp. 27-32, 2009 27th IEEE VLSI Test Symposium, VTS 2009, Santa Cruz, CA, United States, 09/5/3. https://doi.org/10.1109/VTS.2009.25

@inproceedings{43538f1407d245008aea23efeb3b6bb0,

title = "Small delay fault model for intra-gate resistive open defects",

abstract = "We propose the fault model considering weak resistive opens inside the gate which might cause pattern-sequence-dependent and timing-dependent malfunction of the circuit. We assume the fixed observation interval for the signal transition, and derive the minimum resistance of intra-gate resistive opens to be detected as a fault by SPICE simulation. Based on the simulation results, we establish three fault models, that is, the one considering the location of the resistance, the one considering both the location and the resistance distribution, and the simplified one where str and stf faults considering the signal transition of the input ports are assumed. The coverage calculation for the primitive gates and small benchmark circuit reveals that the proposed models have more accuracy on the detection of weak open defects.",

author = "Masayuki Arai and Akifumi Suto and Katsuyuki Nakano and Michihiro Shintani and Kazuhiko Iwasaki and Kazumi Hatayama and Takashi Aikyo",

year = "2009",

doi = "10.1109/VTS.2009.25",

language = "English",

isbn = "9780769535982",

series = "Proceedings of the IEEE VLSI Test Symposium",

pages = "27--32",

booktitle = "Proceedings - 2009 27th IEEE VLSI Test Symposium, VTS 2009",

note = "2009 27th IEEE VLSI Test Symposium, VTS 2009 ; Conference date: 03-05-2009 Through 07-05-2009",

}

TY - GEN

T1 - Small delay fault model for intra-gate resistive open defects

AU - Arai, Masayuki

AU - Suto, Akifumi

AU - Nakano, Katsuyuki

AU - Shintani, Michihiro

AU - Iwasaki, Kazuhiko

AU - Hatayama, Kazumi

AU - Aikyo, Takashi

PY - 2009

Y1 - 2009

N2 - We propose the fault model considering weak resistive opens inside the gate which might cause pattern-sequence-dependent and timing-dependent malfunction of the circuit. We assume the fixed observation interval for the signal transition, and derive the minimum resistance of intra-gate resistive opens to be detected as a fault by SPICE simulation. Based on the simulation results, we establish three fault models, that is, the one considering the location of the resistance, the one considering both the location and the resistance distribution, and the simplified one where str and stf faults considering the signal transition of the input ports are assumed. The coverage calculation for the primitive gates and small benchmark circuit reveals that the proposed models have more accuracy on the detection of weak open defects.

AB - We propose the fault model considering weak resistive opens inside the gate which might cause pattern-sequence-dependent and timing-dependent malfunction of the circuit. We assume the fixed observation interval for the signal transition, and derive the minimum resistance of intra-gate resistive opens to be detected as a fault by SPICE simulation. Based on the simulation results, we establish three fault models, that is, the one considering the location of the resistance, the one considering both the location and the resistance distribution, and the simplified one where str and stf faults considering the signal transition of the input ports are assumed. The coverage calculation for the primitive gates and small benchmark circuit reveals that the proposed models have more accuracy on the detection of weak open defects.

UR - http://www.scopus.com/inward/record.url?scp=70350374214&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=70350374214&partnerID=8YFLogxK

U2 - 10.1109/VTS.2009.25

DO - 10.1109/VTS.2009.25

M3 - Conference contribution

AN - SCOPUS:70350374214

SN - 9780769535982

T3 - Proceedings of the IEEE VLSI Test Symposium

SP - 27

EP - 32

BT - Proceedings - 2009 27th IEEE VLSI Test Symposium, VTS 2009

T2 - 2009 27th IEEE VLSI Test Symposium, VTS 2009

Y2 - 3 May 2009 through 7 May 2009

ER -

Small delay fault model for intra-gate resistive open defects

Abstract

Publication series

Conference

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this