Abstract
Novel device architecture is presented, where surface channel (SC) pMOSFET and buried channel (BC) pMOSFET are fabricated on the same chip without extra process steps. High reliability for negative bias temperature instability (NBTI)/hot carrier injection (HCI) and low noise characteristics are realized by BC structure for I/O and analog circuits, and high-speed and high integration are realized by SC structure for core circuits in System-on-a Chip (SoC).
| Original language | English |
|---|---|
| Pages (from-to) | 869-872 |
| Number of pages | 4 |
| Journal | Technical Digest - International Electron Devices Meeting |
| Publication status | Published - 2001 Dec 1 |
| Event | IEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, United States Duration: 2001 Dec 2 → 2001 Dec 5 |
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ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry
Cite this
Nishida, Y., Sayama, H., Ohta, K., Oda, H., Katayama, M., Inoue, Y., Morimoto, H., & Inuishi, M. (2001). SoC CMOS technology for NBTI/HCI immune I/O and analog circuits implementing surface and buried channel structures. Technical Digest - International Electron Devices Meeting, 869-872.