SoC CMOS technology for NBTI/HCI immune I/O and analog circuits implementing surface and buried channel structures

Y. Nishida, H. Sayama, K. Ohta, H. Oda, M. Katayama, Y. Inoue, H. Morimoto, M. Inuishi

Research output: Contribution to journalConference article

5 Citations (Scopus)

Abstract

Novel device architecture is presented, where surface channel (SC) pMOSFET and buried channel (BC) pMOSFET are fabricated on the same chip without extra process steps. High reliability for negative bias temperature instability (NBTI)/hot carrier injection (HCI) and low noise characteristics are realized by BC structure for I/O and analog circuits, and high-speed and high integration are realized by SC structure for core circuits in System-on-a Chip (SoC).

Original languageEnglish
Pages (from-to)869-872
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 2001 Dec 1
EventIEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, United States
Duration: 2001 Dec 22001 Dec 5

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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