Three-Dimensional Networks-on-Chips (3D-NoCs) have been proposed as an auspicious solution, merging the high parallelism of the Network-on-Chip (NoC) paradigm with the high-performance and low-power of 3D-ICs. However, as feature sizes and power supply voltages continually decrease, the devices and interconnects have become more vulnerable to transient errors. Transient errors, or soft errors, have severe consequences on chip performance, such as deadlock, data corruption, packet loss and increased packet latency. In this paper, we propose a soft-error resilient 3D-NoC router (SER-3DR) architecture for highly-reliable many-core Systems-on-Chips. The proposed architecture is able to recover from transient errors occurring in different pipeline stages of the SER-3DR.We implemented the architecture in hardware with 45 nm CMOS technology. Evaluation results show that SER-3DR is able to achieve a high level of transient error protection with a latency increase of 18.16%, an additional area cost of 14.98% and a power overhead of 5.90% when compared to the baseline router architecture.