Abstract
Three-Dimensional Networks-on-Chips (3D-NoCs) have been proposed as an auspicious solution, merging the high parallelism of the Network-on-Chip (NoC) paradigm with the high-performance and low-power of 3D-ICs. However, as feature sizes and power supply voltages continually decrease, the devices and interconnects have become more vulnerable to transient errors. Transient errors, or soft errors, have severe consequences on chip performance, such as deadlock, data corruption, packet loss and increased packet latency. In this paper, we propose a soft-error resilient 3D-NoC router (SER-3DR) architecture for highly-reliable many-core Systems-on-Chips. The proposed architecture is able to recover from transient errors occurring in different pipeline stages of the SER-3DR.We implemented the architecture in hardware with 45 nm CMOS technology. Evaluation results show that SER-3DR is able to achieve a high level of transient error protection with a latency increase of 18.16%, an additional area cost of 14.98% and a power overhead of 5.90% when compared to the baseline router architecture.
| Original language | English |
|---|---|
| Title of host publication | IEEE 7th International Conference on Awareness Science and Technology, iCAST 2015 - Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 84-90 |
| Number of pages | 7 |
| ISBN (Electronic) | 9781467376587 |
| DOIs | |
| Publication status | Published - 2015 Oct 30 |
| Externally published | Yes |
| Event | 7th IEEE International Conference on Awareness Science and Technology, iCAST 2015 - Qinhuangdao, China Duration: 2015 Sep 22 → 2015 Sep 24 |
Other
| Other | 7th IEEE International Conference on Awareness Science and Technology, iCAST 2015 |
|---|---|
| Country | China |
| City | Qinhuangdao |
| Period | 15/9/22 → 15/9/24 |
Fingerprint
ASJC Scopus subject areas
- Signal Processing
- Computer Networks and Communications
- Computer Vision and Pattern Recognition
Cite this
Soft-error resilient 3D Network-on-Chip router. / Dang, Khanh N.; Meyer, Michael Conrad; Okuyama, Yuichi; Abdallah, Abderazek Ben; Tran, Xuan Tu.
IEEE 7th International Conference on Awareness Science and Technology, iCAST 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2015. p. 84-90 7314025.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Soft-error resilient 3D Network-on-Chip router
AU - Dang, Khanh N.
AU - Meyer, Michael Conrad
AU - Okuyama, Yuichi
AU - Abdallah, Abderazek Ben
AU - Tran, Xuan Tu
PY - 2015/10/30
Y1 - 2015/10/30
N2 - Three-Dimensional Networks-on-Chips (3D-NoCs) have been proposed as an auspicious solution, merging the high parallelism of the Network-on-Chip (NoC) paradigm with the high-performance and low-power of 3D-ICs. However, as feature sizes and power supply voltages continually decrease, the devices and interconnects have become more vulnerable to transient errors. Transient errors, or soft errors, have severe consequences on chip performance, such as deadlock, data corruption, packet loss and increased packet latency. In this paper, we propose a soft-error resilient 3D-NoC router (SER-3DR) architecture for highly-reliable many-core Systems-on-Chips. The proposed architecture is able to recover from transient errors occurring in different pipeline stages of the SER-3DR.We implemented the architecture in hardware with 45 nm CMOS technology. Evaluation results show that SER-3DR is able to achieve a high level of transient error protection with a latency increase of 18.16%, an additional area cost of 14.98% and a power overhead of 5.90% when compared to the baseline router architecture.
AB - Three-Dimensional Networks-on-Chips (3D-NoCs) have been proposed as an auspicious solution, merging the high parallelism of the Network-on-Chip (NoC) paradigm with the high-performance and low-power of 3D-ICs. However, as feature sizes and power supply voltages continually decrease, the devices and interconnects have become more vulnerable to transient errors. Transient errors, or soft errors, have severe consequences on chip performance, such as deadlock, data corruption, packet loss and increased packet latency. In this paper, we propose a soft-error resilient 3D-NoC router (SER-3DR) architecture for highly-reliable many-core Systems-on-Chips. The proposed architecture is able to recover from transient errors occurring in different pipeline stages of the SER-3DR.We implemented the architecture in hardware with 45 nm CMOS technology. Evaluation results show that SER-3DR is able to achieve a high level of transient error protection with a latency increase of 18.16%, an additional area cost of 14.98% and a power overhead of 5.90% when compared to the baseline router architecture.
UR - http://www.scopus.com/inward/record.url?scp=84962106264&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84962106264&partnerID=8YFLogxK
U2 - 10.1109/ICAwST.2015.7314025
DO - 10.1109/ICAwST.2015.7314025
M3 - Conference contribution
AN - SCOPUS:84962106264
SP - 84
EP - 90
BT - IEEE 7th International Conference on Awareness Science and Technology, iCAST 2015 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
ER -