TY - GEN
T1 - Soft-error resilient 3D Network-on-Chip router
AU - Dang, Khanh N.
AU - Meyer, Michael
AU - Okuyama, Yuichi
AU - Abdallah, Abderazek Ben
AU - Tran, Xuan Tu
N1 - Funding Information:
Acknowledgment This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo, Japan, in collaboration with Synopsis, Inc. and Cadence Design Systems, Inc. This project is also supported by Competitive research funding, Ref. UoA-CRF 2014 and P-5 2015, Fukushima, Japan. The work of Xuan-Tu Tran is partially supported by Nafosted under the project No. 102.01-2013.17.
PY - 2015/10/30
Y1 - 2015/10/30
N2 - Three-Dimensional Networks-on-Chips (3D-NoCs) have been proposed as an auspicious solution, merging the high parallelism of the Network-on-Chip (NoC) paradigm with the high-performance and low-power of 3D-ICs. However, as feature sizes and power supply voltages continually decrease, the devices and interconnects have become more vulnerable to transient errors. Transient errors, or soft errors, have severe consequences on chip performance, such as deadlock, data corruption, packet loss and increased packet latency. In this paper, we propose a soft-error resilient 3D-NoC router (SER-3DR) architecture for highly-reliable many-core Systems-on-Chips. The proposed architecture is able to recover from transient errors occurring in different pipeline stages of the SER-3DR.We implemented the architecture in hardware with 45 nm CMOS technology. Evaluation results show that SER-3DR is able to achieve a high level of transient error protection with a latency increase of 18.16%, an additional area cost of 14.98% and a power overhead of 5.90% when compared to the baseline router architecture.
AB - Three-Dimensional Networks-on-Chips (3D-NoCs) have been proposed as an auspicious solution, merging the high parallelism of the Network-on-Chip (NoC) paradigm with the high-performance and low-power of 3D-ICs. However, as feature sizes and power supply voltages continually decrease, the devices and interconnects have become more vulnerable to transient errors. Transient errors, or soft errors, have severe consequences on chip performance, such as deadlock, data corruption, packet loss and increased packet latency. In this paper, we propose a soft-error resilient 3D-NoC router (SER-3DR) architecture for highly-reliable many-core Systems-on-Chips. The proposed architecture is able to recover from transient errors occurring in different pipeline stages of the SER-3DR.We implemented the architecture in hardware with 45 nm CMOS technology. Evaluation results show that SER-3DR is able to achieve a high level of transient error protection with a latency increase of 18.16%, an additional area cost of 14.98% and a power overhead of 5.90% when compared to the baseline router architecture.
UR - http://www.scopus.com/inward/record.url?scp=84962106264&partnerID=8YFLogxK
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U2 - 10.1109/ICAwST.2015.7314025
DO - 10.1109/ICAwST.2015.7314025
M3 - Conference contribution
AN - SCOPUS:84962106264
T3 - IEEE 7th International Conference on Awareness Science and Technology, iCAST 2015 - Proceedings
SP - 84
EP - 90
BT - IEEE 7th International Conference on Awareness Science and Technology, iCAST 2015 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th IEEE International Conference on Awareness Science and Technology, iCAST 2015
Y2 - 22 September 2015 through 24 September 2015
ER -