Soft error tolerant latch designs with low power consumption (invited paper)

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    As semiconductor technology continues scaling down, the reliability issue has become much more critical than ever before. Unlike traditional hard-errors caused by permanent physical damage which can't be recovered in field, soft errors are caused by radiation or voltage/current fluctuations that lead to transient changes on internal node states, thus they can be viewed as temporary errors. However, due to the unpredictable occurrence of soft errors, it is desirable to develop soft error tolerant designs. For this reason, soft error tolerant design techniques have gained great research interest. In this paper, we will explain the soft error mechanism and then review the existing soft error tolerant design techniques with particular emphasis on SEH family because they can achieve low power consumption and small performance overhead as well.

    Original languageEnglish
    Title of host publicationProceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
    PublisherIEEE Computer Society
    Pages52-55
    Number of pages4
    Volume2017-October
    ISBN (Electronic)9781509066247
    DOIs
    Publication statusPublished - 2018 Jan 8
    Event12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 - Guiyang, China
    Duration: 2017 Oct 252017 Oct 28

    Other

    Other12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017
    CountryChina
    CityGuiyang
    Period17/10/2517/10/28

    Fingerprint

    Electric power utilization
    Semiconductor materials
    Radiation
    Electric potential

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Cite this

    Tajima, S., Togawa, N., Yanagisawa, M., & Shi, Y. (2018). Soft error tolerant latch designs with low power consumption (invited paper). In Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017 (Vol. 2017-October, pp. 52-55). IEEE Computer Society. https://doi.org/10.1109/ASICON.2017.8252409

    Soft error tolerant latch designs with low power consumption (invited paper). / Tajima, Saki; Togawa, Nozomu; Yanagisawa, Masao; Shi, Youhua.

    Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. Vol. 2017-October IEEE Computer Society, 2018. p. 52-55.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Tajima, S, Togawa, N, Yanagisawa, M & Shi, Y 2018, Soft error tolerant latch designs with low power consumption (invited paper). in Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. vol. 2017-October, IEEE Computer Society, pp. 52-55, 12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017, Guiyang, China, 17/10/25. https://doi.org/10.1109/ASICON.2017.8252409
    Tajima S, Togawa N, Yanagisawa M, Shi Y. Soft error tolerant latch designs with low power consumption (invited paper). In Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. Vol. 2017-October. IEEE Computer Society. 2018. p. 52-55 https://doi.org/10.1109/ASICON.2017.8252409
    Tajima, Saki ; Togawa, Nozomu ; Yanagisawa, Masao ; Shi, Youhua. / Soft error tolerant latch designs with low power consumption (invited paper). Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. Vol. 2017-October IEEE Computer Society, 2018. pp. 52-55
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