Software-cooperative power-efficient heterogeneous multi-core for media processing

Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

A heterogeneous multi-core processor (HMCP) architecture, which integrates general purpose processors (CPU) and accelerators (ACC) to achieve high-performance as well as low-power consumption with the support of a parallelizing compiler, was developed. The evaluation was performed using an MP3 audio encoder on a simulator that accurately models the HMCP. It showed that 16-frame encoding on the HMCP with four CPUs and four ACCs yielded 24.5-fold speed-up of performance against sequential execution on one CPU. Furthermore, power saving by the compiler reduced energy consumption of the encoding to 0.17 J, namely, by 28.4%.

Original languageEnglish
Title of host publication2008 Asia and South Pacific Design Automation Conference, ASP-DAC
Pages736-741
Number of pages6
DOIs
Publication statusPublished - 2008 Aug 21
Event2008 Asia and South Pacific Design Automation Conference, ASP-DAC - Seoul, Korea, Republic of
Duration: 2008 Mar 212008 Mar 24

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2008 Asia and South Pacific Design Automation Conference, ASP-DAC
Country/TerritoryKorea, Republic of
CitySeoul
Period08/3/2108/3/24

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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