SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

Katsuhiro Suma, Takahiro Tsuruda, Hideto Hidaka, Takahisa Eimori, Toshiyuki Oashi, Yasuo Yamaguchi, Toshiaki Iwamatsu, Masakazu Hirose, Fukashi Morishita, Kazutami Arimoto, Kazuyasu Fujishima, Yasuo Inoue, Tadashi Nishimura, Tsutomu Yoshihara

Research output: Contribution to journalArticle

26 Citations (Scopus)

Abstract

An SOI-DRAM test device (64-Kb scale) with 100-nm-thick SOI film has been fabricated in 0.5-μm CMOS/SIMOX technology and the basic DRAM function has been successfully observed. A partially depleted transistor was used to solve the floating-body effect, resulting in improved operation. The newly introduced body-synchronized sensing scheme enhances the lower Vcc margin. The p-n junction capacitance between source/drain and a substrate for SOI structure is reduced by 25%. RAS access time tRAC is 70 ns with a 2.7-V power supply, which is as fast as the equivalent bulk-Si device with a 4-V power supply. The active current consumption is 1.1 mA (Vcc = 3.0 V, 260-ns cycle) for this SOI-DRAM, which is a reduction of 65%, compared with 3.2 mA for the reference bulk-Si DRAM. The mean value of data retention time for this chip at 80 °C is longer than 20 s (Vcc = 3.3 V), which is the same value as mass-produced 16-Mb DRAM's. The SOI-DRAM has an operating Vcc range from 2.3 V to 4.0 V. The observed speed enhancement and the wide operating voltage range indicate high performance at the low voltage operation suitable for battery-operated DRAM's.

Original languageEnglish
Pages (from-to)1323-1329
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Volume29
Issue number11
DOIs
Publication statusPublished - 1994 Nov
Externally publishedYes

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Dynamic random access storage
Electric potential
Thick films
Transistors
Capacitance
Substrates

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Suma, K., Tsuruda, T., Hidaka, H., Eimori, T., Oashi, T., Yamaguchi, Y., ... Yoshihara, T. (1994). SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. IEEE Journal of Solid-State Circuits, 29(11), 1323-1329. https://doi.org/10.1109/4.328631

SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. / Suma, Katsuhiro; Tsuruda, Takahiro; Hidaka, Hideto; Eimori, Takahisa; Oashi, Toshiyuki; Yamaguchi, Yasuo; Iwamatsu, Toshiaki; Hirose, Masakazu; Morishita, Fukashi; Arimoto, Kazutami; Fujishima, Kazuyasu; Inoue, Yasuo; Nishimura, Tadashi; Yoshihara, Tsutomu.

In: IEEE Journal of Solid-State Circuits, Vol. 29, No. 11, 11.1994, p. 1323-1329.

Research output: Contribution to journalArticle

Suma, K, Tsuruda, T, Hidaka, H, Eimori, T, Oashi, T, Yamaguchi, Y, Iwamatsu, T, Hirose, M, Morishita, F, Arimoto, K, Fujishima, K, Inoue, Y, Nishimura, T & Yoshihara, T 1994, 'SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology', IEEE Journal of Solid-State Circuits, vol. 29, no. 11, pp. 1323-1329. https://doi.org/10.1109/4.328631
Suma K, Tsuruda T, Hidaka H, Eimori T, Oashi T, Yamaguchi Y et al. SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. IEEE Journal of Solid-State Circuits. 1994 Nov;29(11):1323-1329. https://doi.org/10.1109/4.328631
Suma, Katsuhiro ; Tsuruda, Takahiro ; Hidaka, Hideto ; Eimori, Takahisa ; Oashi, Toshiyuki ; Yamaguchi, Yasuo ; Iwamatsu, Toshiaki ; Hirose, Masakazu ; Morishita, Fukashi ; Arimoto, Kazutami ; Fujishima, Kazuyasu ; Inoue, Yasuo ; Nishimura, Tadashi ; Yoshihara, Tsutomu. / SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. In: IEEE Journal of Solid-State Circuits. 1994 ; Vol. 29, No. 11. pp. 1323-1329.
@article{77af1f39d79d40d782ee9d36b234db38,
title = "SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology",
abstract = "An SOI-DRAM test device (64-Kb scale) with 100-nm-thick SOI film has been fabricated in 0.5-μm CMOS/SIMOX technology and the basic DRAM function has been successfully observed. A partially depleted transistor was used to solve the floating-body effect, resulting in improved operation. The newly introduced body-synchronized sensing scheme enhances the lower Vcc margin. The p-n junction capacitance between source/drain and a substrate for SOI structure is reduced by 25{\%}. RAS access time tRAC is 70 ns with a 2.7-V power supply, which is as fast as the equivalent bulk-Si device with a 4-V power supply. The active current consumption is 1.1 mA (Vcc = 3.0 V, 260-ns cycle) for this SOI-DRAM, which is a reduction of 65{\%}, compared with 3.2 mA for the reference bulk-Si DRAM. The mean value of data retention time for this chip at 80 °C is longer than 20 s (Vcc = 3.3 V), which is the same value as mass-produced 16-Mb DRAM's. The SOI-DRAM has an operating Vcc range from 2.3 V to 4.0 V. The observed speed enhancement and the wide operating voltage range indicate high performance at the low voltage operation suitable for battery-operated DRAM's.",
author = "Katsuhiro Suma and Takahiro Tsuruda and Hideto Hidaka and Takahisa Eimori and Toshiyuki Oashi and Yasuo Yamaguchi and Toshiaki Iwamatsu and Masakazu Hirose and Fukashi Morishita and Kazutami Arimoto and Kazuyasu Fujishima and Yasuo Inoue and Tadashi Nishimura and Tsutomu Yoshihara",
year = "1994",
month = "11",
doi = "10.1109/4.328631",
language = "English",
volume = "29",
pages = "1323--1329",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "11",

}

TY - JOUR

T1 - SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

AU - Suma, Katsuhiro

AU - Tsuruda, Takahiro

AU - Hidaka, Hideto

AU - Eimori, Takahisa

AU - Oashi, Toshiyuki

AU - Yamaguchi, Yasuo

AU - Iwamatsu, Toshiaki

AU - Hirose, Masakazu

AU - Morishita, Fukashi

AU - Arimoto, Kazutami

AU - Fujishima, Kazuyasu

AU - Inoue, Yasuo

AU - Nishimura, Tadashi

AU - Yoshihara, Tsutomu

PY - 1994/11

Y1 - 1994/11

N2 - An SOI-DRAM test device (64-Kb scale) with 100-nm-thick SOI film has been fabricated in 0.5-μm CMOS/SIMOX technology and the basic DRAM function has been successfully observed. A partially depleted transistor was used to solve the floating-body effect, resulting in improved operation. The newly introduced body-synchronized sensing scheme enhances the lower Vcc margin. The p-n junction capacitance between source/drain and a substrate for SOI structure is reduced by 25%. RAS access time tRAC is 70 ns with a 2.7-V power supply, which is as fast as the equivalent bulk-Si device with a 4-V power supply. The active current consumption is 1.1 mA (Vcc = 3.0 V, 260-ns cycle) for this SOI-DRAM, which is a reduction of 65%, compared with 3.2 mA for the reference bulk-Si DRAM. The mean value of data retention time for this chip at 80 °C is longer than 20 s (Vcc = 3.3 V), which is the same value as mass-produced 16-Mb DRAM's. The SOI-DRAM has an operating Vcc range from 2.3 V to 4.0 V. The observed speed enhancement and the wide operating voltage range indicate high performance at the low voltage operation suitable for battery-operated DRAM's.

AB - An SOI-DRAM test device (64-Kb scale) with 100-nm-thick SOI film has been fabricated in 0.5-μm CMOS/SIMOX technology and the basic DRAM function has been successfully observed. A partially depleted transistor was used to solve the floating-body effect, resulting in improved operation. The newly introduced body-synchronized sensing scheme enhances the lower Vcc margin. The p-n junction capacitance between source/drain and a substrate for SOI structure is reduced by 25%. RAS access time tRAC is 70 ns with a 2.7-V power supply, which is as fast as the equivalent bulk-Si device with a 4-V power supply. The active current consumption is 1.1 mA (Vcc = 3.0 V, 260-ns cycle) for this SOI-DRAM, which is a reduction of 65%, compared with 3.2 mA for the reference bulk-Si DRAM. The mean value of data retention time for this chip at 80 °C is longer than 20 s (Vcc = 3.3 V), which is the same value as mass-produced 16-Mb DRAM's. The SOI-DRAM has an operating Vcc range from 2.3 V to 4.0 V. The observed speed enhancement and the wide operating voltage range indicate high performance at the low voltage operation suitable for battery-operated DRAM's.

UR - http://www.scopus.com/inward/record.url?scp=0028542559&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028542559&partnerID=8YFLogxK

U2 - 10.1109/4.328631

DO - 10.1109/4.328631

M3 - Article

AN - SCOPUS:0028542559

VL - 29

SP - 1323

EP - 1329

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 11

ER -