SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

Katsuhiro Suma; Takahiro Tsuruda; Hideto Hidaka; Takahisa Eimori; Toshiyuki Oashi; Yasuo Yamaguchi; Toshiaki Iwamatsu; Masakazu Hirose; Kazuyasy Fujishima; Yasuro Inoue; Tadashi Nishimura; Tsutomu Yoshihara

SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

Katsuhiro Suma, Takahiro Tsuruda, Hideto Hidaka, Takahisa Eimori, Toshiyuki Oashi, Yasuo Yamaguchi, Toshiaki Iwamatsu, Masakazu Hirose, Kazuyasy Fujishima, Yasuro Inoue, Tadashi Nishimura, Tsutomu Yoshihara

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Citations (Scopus)

Abstract

The fundamental limitations of the SOI and bulk-Si DRAM are compared at 1.5V Vcc operation. The dependence of the read out signal amplitude on the memory cell storage capacitance (Cs) is shown. It is assumed that bit-line capacitance Cb of SOI structures i reduced by 25% compared with that of bulk-Si substrates. The mean value of data retention time in 256Mb DRAM should be longer than 5s at 80°C. For both memory cell structures, p-n junction leakage current is the dominant leakage mechanism. For 1.5V operation the lower limit of memory cell capacitance (Cs) from the data retention requirement is only 4.5fF for SOI, contrasted with 24fF for bulk-Si. This is because the junction area of SOI memory cell is reduced to 7.5% of bulk-Si DDRAM. Therefore thin-film SOL-DRAM provides a great advantage in data retention.

Original language	English
Title of host publication	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Editors	Anon
Place of Publication	Piscataway, NJ, United States
Publisher	Publ by IEEE
Pages	138-139
Number of pages	2
ISBN (Print)	0780318455
Publication status	Published - 1994
Externally published	Yes
Event	Proceedings of the 1994 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA Duration: 1994 Feb 16 → 1994 Feb 18

Other

Other	Proceedings of the 1994 IEEE International Solid-State Circuits Conference
City	San Francisco, CA, USA
Period	94/2/16 → 94/2/18

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Engineering(all)

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SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. / Suma, Katsuhiro; Tsuruda, Takahiro; Hidaka, Hideto; Eimori, Takahisa; Oashi, Toshiyuki; Yamaguchi, Yasuo; Iwamatsu, Toshiaki; Hirose, Masakazu; Fujishima, Kazuyasy; Inoue, Yasuro; Nishimura, Tadashi; Yoshihara, Tsutomu.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. ed. / Anon. Piscataway, NJ, United States : Publ by IEEE, 1994. p. 138-139.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Suma, K, Tsuruda, T, Hidaka, H, Eimori, T, Oashi, T, Yamaguchi, Y, Iwamatsu, T, Hirose, M, Fujishima, K, Inoue, Y, Nishimura, T & Yoshihara, T 1994, SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. in Anon (ed.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Publ by IEEE, Piscataway, NJ, United States, pp. 138-139, Proceedings of the 1994 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 94/2/16.

Suma, Katsuhiro ; Tsuruda, Takahiro ; Hidaka, Hideto ; Eimori, Takahisa ; Oashi, Toshiyuki ; Yamaguchi, Yasuo ; Iwamatsu, Toshiaki ; Hirose, Masakazu ; Fujishima, Kazuyasy ; Inoue, Yasuro ; Nishimura, Tadashi ; Yoshihara, Tsutomu. / SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. editor / Anon. Piscataway, NJ, United States : Publ by IEEE, 1994. pp. 138-139

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abstract = "The fundamental limitations of the SOI and bulk-Si DRAM are compared at 1.5V Vcc operation. The dependence of the read out signal amplitude on the memory cell storage capacitance (Cs) is shown. It is assumed that bit-line capacitance Cb of SOI structures i reduced by 25% compared with that of bulk-Si substrates. The mean value of data retention time in 256Mb DRAM should be longer than 5s at 80°C. For both memory cell structures, p-n junction leakage current is the dominant leakage mechanism. For 1.5V operation the lower limit of memory cell capacitance (Cs) from the data retention requirement is only 4.5fF for SOI, contrasted with 24fF for bulk-Si. This is because the junction area of SOI memory cell is reduced to 7.5% of bulk-Si DDRAM. Therefore thin-film SOL-DRAM provides a great advantage in data retention.",

author = "Katsuhiro Suma and Takahiro Tsuruda and Hideto Hidaka and Takahisa Eimori and Toshiyuki Oashi and Yasuo Yamaguchi and Toshiaki Iwamatsu and Masakazu Hirose and Kazuyasy Fujishima and Yasuro Inoue and Tadashi Nishimura and Tsutomu Yoshihara",

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AU - Oashi, Toshiyuki

AU - Yamaguchi, Yasuo

AU - Iwamatsu, Toshiaki

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AU - Nishimura, Tadashi

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N2 - The fundamental limitations of the SOI and bulk-Si DRAM are compared at 1.5V Vcc operation. The dependence of the read out signal amplitude on the memory cell storage capacitance (Cs) is shown. It is assumed that bit-line capacitance Cb of SOI structures i reduced by 25% compared with that of bulk-Si substrates. The mean value of data retention time in 256Mb DRAM should be longer than 5s at 80°C. For both memory cell structures, p-n junction leakage current is the dominant leakage mechanism. For 1.5V operation the lower limit of memory cell capacitance (Cs) from the data retention requirement is only 4.5fF for SOI, contrasted with 24fF for bulk-Si. This is because the junction area of SOI memory cell is reduced to 7.5% of bulk-Si DDRAM. Therefore thin-film SOL-DRAM provides a great advantage in data retention.

AB - The fundamental limitations of the SOI and bulk-Si DRAM are compared at 1.5V Vcc operation. The dependence of the read out signal amplitude on the memory cell storage capacitance (Cs) is shown. It is assumed that bit-line capacitance Cb of SOI structures i reduced by 25% compared with that of bulk-Si substrates. The mean value of data retention time in 256Mb DRAM should be longer than 5s at 80°C. For both memory cell structures, p-n junction leakage current is the dominant leakage mechanism. For 1.5V operation the lower limit of memory cell capacitance (Cs) from the data retention requirement is only 4.5fF for SOI, contrasted with 24fF for bulk-Si. This is because the junction area of SOI memory cell is reduced to 7.5% of bulk-Si DDRAM. Therefore thin-film SOL-DRAM provides a great advantage in data retention.

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