Source-line programming scheme for low voltage operation NAND flash memories

Ken Takeuchi; Shinji Satoh; Kenichi Imamiya; Yoshihisa Sugiura; Hiroshi Nakamura; Toshihiko Himeno; Tamio Ikehashi; Kazushige Kanda; Koji Hosono; Koji Sakui

Source-line programming scheme for low voltage operation NAND flash memories

Ken Takeuchi, Shinji Satoh, Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Koji Sakui

Research output: Contribution to conference › Paper › peer-review

9 Citations (Scopus)

Abstract

Proposed is a new programming scheme that drastically reduces the program disturb and realizes highly reliable, high-speed programming, low voltage operation, low power consumption and low cost NAND flash memories. This scheme has been realized in a 256Mb test device using a 0.25μm CMOS-STI technology.

Original language	English
Pages	37-38
Number of pages	2
Publication status	Published - 1999 Dec 1
Externally published	Yes
Event	Proceedings of the 1999 Symposium on VLSI Circuits - Kyoto, Jpn Duration: 1999 Jun 17 → 1999 Jun 19

Conference

Conference	Proceedings of the 1999 Symposium on VLSI Circuits
City	Kyoto, Jpn
Period	99/6/17 → 99/6/19

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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Source-line programming scheme for low voltage operation NAND flash memories. / Takeuchi, Ken; Satoh, Shinji; Imamiya, Kenichi; Sugiura, Yoshihisa; Nakamura, Hiroshi; Himeno, Toshihiko; Ikehashi, Tamio; Kanda, Kazushige; Hosono, Koji; Sakui, Koji.

1999. 37-38 Paper presented at Proceedings of the 1999 Symposium on VLSI Circuits, Kyoto, Jpn, .

Research output: Contribution to conference › Paper › peer-review

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title = "Source-line programming scheme for low voltage operation NAND flash memories",

abstract = "Proposed is a new programming scheme that drastically reduces the program disturb and realizes highly reliable, high-speed programming, low voltage operation, low power consumption and low cost NAND flash memories. This scheme has been realized in a 256Mb test device using a 0.25μm CMOS-STI technology.",

author = "Ken Takeuchi and Shinji Satoh and Kenichi Imamiya and Yoshihisa Sugiura and Hiroshi Nakamura and Toshihiko Himeno and Tamio Ikehashi and Kazushige Kanda and Koji Hosono and Koji Sakui",

year = "1999",

month = dec,

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pages = "37--38",

note = "Proceedings of the 1999 Symposium on VLSI Circuits ; Conference date: 17-06-1999 Through 19-06-1999",

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TY - CONF

T1 - Source-line programming scheme for low voltage operation NAND flash memories

AU - Takeuchi, Ken

AU - Satoh, Shinji

AU - Imamiya, Kenichi

AU - Sugiura, Yoshihisa

AU - Nakamura, Hiroshi

AU - Himeno, Toshihiko

AU - Ikehashi, Tamio

AU - Kanda, Kazushige

AU - Hosono, Koji

AU - Sakui, Koji

PY - 1999/12/1

Y1 - 1999/12/1

N2 - Proposed is a new programming scheme that drastically reduces the program disturb and realizes highly reliable, high-speed programming, low voltage operation, low power consumption and low cost NAND flash memories. This scheme has been realized in a 256Mb test device using a 0.25μm CMOS-STI technology.

AB - Proposed is a new programming scheme that drastically reduces the program disturb and realizes highly reliable, high-speed programming, low voltage operation, low power consumption and low cost NAND flash memories. This scheme has been realized in a 256Mb test device using a 0.25μm CMOS-STI technology.

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UR - http://www.scopus.com/inward/citedby.url?scp=0033281038&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0033281038

SP - 37

EP - 38

T2 - Proceedings of the 1999 Symposium on VLSI Circuits

Y2 - 17 June 1999 through 19 June 1999

ER -

Source-line programming scheme for low voltage operation NAND flash memories

Abstract

Conference

ASJC Scopus subject areas

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