Abstract
Proposed is a new programming scheme that drastically reduces the program disturb and realizes highly reliable, high-speed programming, low voltage operation, low power consumption and low cost NAND flash memories. This scheme has been realized in a 256Mb test device using a 0.25μm CMOS-STI technology.
| Original language | English |
|---|---|
| Pages | 37-38 |
| Number of pages | 2 |
| Publication status | Published - 1999 Dec 1 |
| Externally published | Yes |
| Event | Proceedings of the 1999 Symposium on VLSI Circuits - Kyoto, Jpn Duration: 1999 Jun 17 → 1999 Jun 19 |
Conference
| Conference | Proceedings of the 1999 Symposium on VLSI Circuits |
|---|---|
| City | Kyoto, Jpn |
| Period | 99/6/17 → 99/6/19 |
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ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
Source-line programming scheme for low voltage operation NAND flash memories. / Takeuchi, Ken; Satoh, Shinji; Imamiya, Kenichi; Sugiura, Yoshihisa; Nakamura, Hiroshi; Himeno, Toshihiko; Ikehashi, Tamio; Kanda, Kazushige; Hosono, Koji; Sakui, Koji.
1999. 37-38 Paper presented at Proceedings of the 1999 Symposium on VLSI Circuits, Kyoto, Jpn, .Research output: Contribution to conference › Paper
}
TY - CONF
T1 - Source-line programming scheme for low voltage operation NAND flash memories
AU - Takeuchi, Ken
AU - Satoh, Shinji
AU - Imamiya, Kenichi
AU - Sugiura, Yoshihisa
AU - Nakamura, Hiroshi
AU - Himeno, Toshihiko
AU - Ikehashi, Tamio
AU - Kanda, Kazushige
AU - Hosono, Koji
AU - Sakui, Koji
PY - 1999/12/1
Y1 - 1999/12/1
N2 - Proposed is a new programming scheme that drastically reduces the program disturb and realizes highly reliable, high-speed programming, low voltage operation, low power consumption and low cost NAND flash memories. This scheme has been realized in a 256Mb test device using a 0.25μm CMOS-STI technology.
AB - Proposed is a new programming scheme that drastically reduces the program disturb and realizes highly reliable, high-speed programming, low voltage operation, low power consumption and low cost NAND flash memories. This scheme has been realized in a 256Mb test device using a 0.25μm CMOS-STI technology.
UR - http://www.scopus.com/inward/record.url?scp=0033281038&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0033281038&partnerID=8YFLogxK
M3 - Paper
SP - 37
EP - 38
ER -