Source-line programming scheme for low voltage operation NAND flash memories

Ken Takeuchi*, Shinji Satoh, Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Koji Sakui

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

9 Citations (Scopus)

Abstract

Proposed is a new programming scheme that drastically reduces the program disturb and realizes highly reliable, high-speed programming, low voltage operation, low power consumption and low cost NAND flash memories. This scheme has been realized in a 256Mb test device using a 0.25μm CMOS-STI technology.

Original languageEnglish
Pages37-38
Number of pages2
Publication statusPublished - 1999
Externally publishedYes
EventProceedings of the 1999 Symposium on VLSI Circuits - Kyoto, Jpn
Duration: 1999 Jun 171999 Jun 19

Conference

ConferenceProceedings of the 1999 Symposium on VLSI Circuits
CityKyoto, Jpn
Period99/6/1799/6/19

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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