Spatial feature based reconfigurable H.264/AVC integer motion estimation architecture for HDTV video encoder

Yiqing Huang, Qin Liu, Takeshi Ikenaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In this paper, we contribute one reconfigurable integer motion estimation (IME) architectures (namely RPPSAD) based on adaptive algorithm. Firstly, based on the pixel difference analysis, the spatial redundancy is further exploited and three subsampling patterns are selected adaptively for the IME process. Secondly, in order to achieve data reuse and power reduction in memory part, the reference pixels in search window are reorganization into two memory groups, which output pixel data interactively for adaptive subsampling. Moreover, a compressor tree based circuit level optimization is included in our design to reduce hardware cost. Synthesized with TSMC 0.18um technology, averagely 10k gates hardware can be reduced for the whole IME engine based on our optimization. With 481k gates at 110.5MHz, one 720-p, 30-fps HDTV integer motion estimation engine is designed. Compared with previous work, our design can achieve 39.8% reduction in power consumption with only 3.44% increase in hardware.

Original languageEnglish
Title of host publicationDSP 2009: 16th International Conference on Digital Signal Processing, Proceedings
DOIs
Publication statusPublished - 2009
EventDSP 2009:16th International Conference on Digital Signal Processing - Santorini
Duration: 2009 Jul 52009 Jul 7

Other

OtherDSP 2009:16th International Conference on Digital Signal Processing
CitySantorini
Period09/7/509/7/7

Fingerprint

High definition television
Motion estimation
Pixels
Hardware
Engines
Data storage equipment
Adaptive algorithms
Redundancy
Compressors
Electric power utilization
Networks (circuits)
Costs

Keywords

  • H.264/AVC
  • IME
  • Reconfigurable Structure

ASJC Scopus subject areas

  • Computer Vision and Pattern Recognition
  • Signal Processing

Cite this

Huang, Y., Liu, Q., & Ikenaga, T. (2009). Spatial feature based reconfigurable H.264/AVC integer motion estimation architecture for HDTV video encoder. In DSP 2009: 16th International Conference on Digital Signal Processing, Proceedings [5201185] https://doi.org/10.1109/ICDSP.2009.5201185

Spatial feature based reconfigurable H.264/AVC integer motion estimation architecture for HDTV video encoder. / Huang, Yiqing; Liu, Qin; Ikenaga, Takeshi.

DSP 2009: 16th International Conference on Digital Signal Processing, Proceedings. 2009. 5201185.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Huang, Y, Liu, Q & Ikenaga, T 2009, Spatial feature based reconfigurable H.264/AVC integer motion estimation architecture for HDTV video encoder. in DSP 2009: 16th International Conference on Digital Signal Processing, Proceedings., 5201185, DSP 2009:16th International Conference on Digital Signal Processing, Santorini, 09/7/5. https://doi.org/10.1109/ICDSP.2009.5201185
Huang Y, Liu Q, Ikenaga T. Spatial feature based reconfigurable H.264/AVC integer motion estimation architecture for HDTV video encoder. In DSP 2009: 16th International Conference on Digital Signal Processing, Proceedings. 2009. 5201185 https://doi.org/10.1109/ICDSP.2009.5201185
Huang, Yiqing ; Liu, Qin ; Ikenaga, Takeshi. / Spatial feature based reconfigurable H.264/AVC integer motion estimation architecture for HDTV video encoder. DSP 2009: 16th International Conference on Digital Signal Processing, Proceedings. 2009.
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