Static error analysis and optimization of faithfully truncated adders for area-power efficient FIR designs

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Faithfully truncated adders are used for low cost FIR implementations in this paper, which improves state-of-the-art CSD-based FIR filter designs for further area and power reduction while meeting the accuracy requirement. As a solution to the accuracy loss caused by truncated adders, this paper performed a static error analysis of truncated adders. Furthermore, based upon our mathematical analysis, we show that, with a given accuracy constraint, an optimal truncated adder configuration can be effortlessly determined for area-power efficient FIR designs. Evaluation results on various FIR designs showed that 16.8%~35.4% reduction in area and 11.8%~27.9% in power saving can be achieved with the proposed optimal truncated adder designs within an average error of 1 ulp.

Original languageEnglish
Title of host publication2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728103976
DOIs
Publication statusPublished - 2019 Jan 1
Event2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan
Duration: 2019 May 262019 May 29

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2019-May
ISSN (Print)0271-4310

Conference

Conference2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
CountryJapan
CitySapporo
Period19/5/2619/5/29

Fingerprint

Adders
Error analysis
FIR filters
Costs

Keywords

  • Approximate computing
  • Area-power efficient
  • FIR filter
  • Low cost
  • Truncated adder

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Ye, J., Togawa, N., Yanagisawa, M., & Shi, Y. (2019). Static error analysis and optimization of faithfully truncated adders for area-power efficient FIR designs. In 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings [8702386] (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2019-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2019.8702386

Static error analysis and optimization of faithfully truncated adders for area-power efficient FIR designs. / Ye, Jinghao; Togawa, Nozomu; Yanagisawa, Masao; Shi, Youhua.

2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. 8702386 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2019-May).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ye, J, Togawa, N, Yanagisawa, M & Shi, Y 2019, Static error analysis and optimization of faithfully truncated adders for area-power efficient FIR designs. in 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings., 8702386, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2019-May, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, 19/5/26. https://doi.org/10.1109/ISCAS.2019.8702386
Ye J, Togawa N, Yanagisawa M, Shi Y. Static error analysis and optimization of faithfully truncated adders for area-power efficient FIR designs. In 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2019. 8702386. (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2019.8702386
Ye, Jinghao ; Togawa, Nozomu ; Yanagisawa, Masao ; Shi, Youhua. / Static error analysis and optimization of faithfully truncated adders for area-power efficient FIR designs. 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. (Proceedings - IEEE International Symposium on Circuits and Systems).
@inproceedings{4affb5c8ed5c47a5ad657d7bf9f60f5e,
title = "Static error analysis and optimization of faithfully truncated adders for area-power efficient FIR designs",
abstract = "Faithfully truncated adders are used for low cost FIR implementations in this paper, which improves state-of-the-art CSD-based FIR filter designs for further area and power reduction while meeting the accuracy requirement. As a solution to the accuracy loss caused by truncated adders, this paper performed a static error analysis of truncated adders. Furthermore, based upon our mathematical analysis, we show that, with a given accuracy constraint, an optimal truncated adder configuration can be effortlessly determined for area-power efficient FIR designs. Evaluation results on various FIR designs showed that 16.8{\%}~35.4{\%} reduction in area and 11.8{\%}~27.9{\%} in power saving can be achieved with the proposed optimal truncated adder designs within an average error of 1 ulp.",
keywords = "Approximate computing, Area-power efficient, FIR filter, Low cost, Truncated adder",
author = "Jinghao Ye and Nozomu Togawa and Masao Yanagisawa and Youhua Shi",
year = "2019",
month = "1",
day = "1",
doi = "10.1109/ISCAS.2019.8702386",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings",

}

TY - GEN

T1 - Static error analysis and optimization of faithfully truncated adders for area-power efficient FIR designs

AU - Ye, Jinghao

AU - Togawa, Nozomu

AU - Yanagisawa, Masao

AU - Shi, Youhua

PY - 2019/1/1

Y1 - 2019/1/1

N2 - Faithfully truncated adders are used for low cost FIR implementations in this paper, which improves state-of-the-art CSD-based FIR filter designs for further area and power reduction while meeting the accuracy requirement. As a solution to the accuracy loss caused by truncated adders, this paper performed a static error analysis of truncated adders. Furthermore, based upon our mathematical analysis, we show that, with a given accuracy constraint, an optimal truncated adder configuration can be effortlessly determined for area-power efficient FIR designs. Evaluation results on various FIR designs showed that 16.8%~35.4% reduction in area and 11.8%~27.9% in power saving can be achieved with the proposed optimal truncated adder designs within an average error of 1 ulp.

AB - Faithfully truncated adders are used for low cost FIR implementations in this paper, which improves state-of-the-art CSD-based FIR filter designs for further area and power reduction while meeting the accuracy requirement. As a solution to the accuracy loss caused by truncated adders, this paper performed a static error analysis of truncated adders. Furthermore, based upon our mathematical analysis, we show that, with a given accuracy constraint, an optimal truncated adder configuration can be effortlessly determined for area-power efficient FIR designs. Evaluation results on various FIR designs showed that 16.8%~35.4% reduction in area and 11.8%~27.9% in power saving can be achieved with the proposed optimal truncated adder designs within an average error of 1 ulp.

KW - Approximate computing

KW - Area-power efficient

KW - FIR filter

KW - Low cost

KW - Truncated adder

UR - http://www.scopus.com/inward/record.url?scp=85066804069&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85066804069&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2019.8702386

DO - 10.1109/ISCAS.2019.8702386

M3 - Conference contribution

AN - SCOPUS:85066804069

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

ER -