We propose a strategy for improving the response speed of electric double-layer capacitors (EDLCs) and electric double-layer transistors (EDLTs), based on an asymmetric structure with differently sized active materials and gate electrodes. We validate the strategy analytically by a classical calculation and experimentally by fabricating EDLCs with asymmetric Au electrodes (1:50 area ratio and 7.5 μm gap distance). The performance of the EDLCs is compared with that of conventional symmetric EDLCs. Our strategy dramatically improved the cut-off frequency from 14 to 93 kHz and this improvement is explained by fast charging of smaller electrodes. Therefore, this approach is particularly suitable to EDLTs, potentially expanding the applicability to medium speed (kHz-MHz) devices.
ASJC Scopus subject areas
- Physics and Astronomy (miscellaneous)