TY - JOUR
T1 - Study of self-aligned doped channel MOSFET structure for low power and low 1/f noise operation
AU - Yoshitomi, Takashi
AU - Kimijima, Hideki
AU - Ishizuka, Shinnichiro
AU - Miyahara, Yasunori
AU - Ohguro, Tatsuya
AU - Morifuji, Eiji
AU - Morimoto, Toyota
AU - Sasaki Momose, Hisayo
AU - Katsumata, Yasuhiro
AU - Iwai, Hiroshi
PY - 1999/7
Y1 - 1999/7
N2 - A self-Aligned Doped Channel (SADC) is proposed and investigated for the first time. In the SADC process, the channel doping process is carried out by using solid phase diffusion from the gate; hence the doping region is fully self-aligned to the gate, and the junction capacitance can be reduced. In addition, the implantation damage in the channel is reduced. We obtained 0.25 μm gate length nMOSFETs with low noise and low power consumption by using the SADC structure. Hence, this structure is attractive for small geometry RF CMOS devices.
AB - A self-Aligned Doped Channel (SADC) is proposed and investigated for the first time. In the SADC process, the channel doping process is carried out by using solid phase diffusion from the gate; hence the doping region is fully self-aligned to the gate, and the junction capacitance can be reduced. In addition, the implantation damage in the channel is reduced. We obtained 0.25 μm gate length nMOSFETs with low noise and low power consumption by using the SADC structure. Hence, this structure is attractive for small geometry RF CMOS devices.
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U2 - 10.1016/S0038-1101(99)00066-0
DO - 10.1016/S0038-1101(99)00066-0
M3 - Article
AN - SCOPUS:0032630536
SN - 0038-1101
VL - 43
SP - 1219
EP - 1224
JO - Solid-State Electronics
JF - Solid-State Electronics
IS - 7
ER -