Sub-1 μm2 high density embedded SRAM technologies for 100 nm generation SOC and beyond

K. Tomita, K. Hashimoto, T. Inbe, T. Oashi, K. Tsukamoto, Y. Nishioka, M. Matsuura, T. Eimori, M. Inuishi, I. Miyanaga, M. Nakamura, T. Kishimoto, T. Yamada, K. Eriguchi, H. Yuasa, T. Satake, A. Kajiya, M. Ogura

Research output: Contribution to conferencePaper

9 Citations (Scopus)

Abstract

High density 6T-SRAM cell (0.998 μm2) was integrated for system-on-a-chip using enhanced 100 nm CMOS logic technology. The integration methodology included high-NA ArF lithography, optimized optical proximity correction CAD, narrow well isolation, poly-buffered shallow trench isolation and low-k dielectric technologies. This enhanced SRAM technology could be used for high speed and high density embedded memory applications.

Original languageEnglish
Pages14-15
Number of pages2
Publication statusPublished - 2002 Jan 1
Externally publishedYes
Event2002 Symposium on VLSI Technology Digest of Technical Papers - Honolulu, HI, United States
Duration: 2002 Jun 112002 Jun 13

Other

Other2002 Symposium on VLSI Technology Digest of Technical Papers
CountryUnited States
CityHonolulu, HI
Period02/6/1102/6/13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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