Sub-1 μm2 high density embedded SRAM technologies for 100 nm generation SOC and beyond

K. Tomita, K. Hashimoto, T. Inbe, T. Oashi, K. Tsukamoto, Y. Nishioka, M. Matsuura, T. Eimori, Masahide Inuishi, I. Miyanaga, M. Nakamura, T. Kishimoto, T. Yamada, K. Eriguchi, H. Yuasa, T. Satake, A. Kajiya, M. Ogura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

High density 6T-SRAM cell (0.998 μm2) was integrated for system-on-a-chip using enhanced 100 nm CMOS logic technology. The integration methodology included high-NA ArF lithography, optimized optical proximity correction CAD, narrow well isolation, poly-buffered shallow trench isolation and low-k dielectric technologies. This enhanced SRAM technology could be used for high speed and high density embedded memory applications.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages14-15
Number of pages2
Publication statusPublished - 2002
Externally publishedYes
Event2002 Symposium on VLSI Technology Digest of Technical Papers - Honolulu, HI, United States
Duration: 2002 Jun 112002 Jun 13

Other

Other2002 Symposium on VLSI Technology Digest of Technical Papers
CountryUnited States
CityHonolulu, HI
Period02/6/1102/6/13

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Static random access storage
Photolithography
Computer aided design
Data storage equipment

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Tomita, K., Hashimoto, K., Inbe, T., Oashi, T., Tsukamoto, K., Nishioka, Y., ... Ogura, M. (2002). Sub-1 μm2 high density embedded SRAM technologies for 100 nm generation SOC and beyond. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 14-15)

Sub-1 μm2 high density embedded SRAM technologies for 100 nm generation SOC and beyond. / Tomita, K.; Hashimoto, K.; Inbe, T.; Oashi, T.; Tsukamoto, K.; Nishioka, Y.; Matsuura, M.; Eimori, T.; Inuishi, Masahide; Miyanaga, I.; Nakamura, M.; Kishimoto, T.; Yamada, T.; Eriguchi, K.; Yuasa, H.; Satake, T.; Kajiya, A.; Ogura, M.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2002. p. 14-15.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tomita, K, Hashimoto, K, Inbe, T, Oashi, T, Tsukamoto, K, Nishioka, Y, Matsuura, M, Eimori, T, Inuishi, M, Miyanaga, I, Nakamura, M, Kishimoto, T, Yamada, T, Eriguchi, K, Yuasa, H, Satake, T, Kajiya, A & Ogura, M 2002, Sub-1 μm2 high density embedded SRAM technologies for 100 nm generation SOC and beyond. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers. pp. 14-15, 2002 Symposium on VLSI Technology Digest of Technical Papers, Honolulu, HI, United States, 02/6/11.
Tomita K, Hashimoto K, Inbe T, Oashi T, Tsukamoto K, Nishioka Y et al. Sub-1 μm2 high density embedded SRAM technologies for 100 nm generation SOC and beyond. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2002. p. 14-15
Tomita, K. ; Hashimoto, K. ; Inbe, T. ; Oashi, T. ; Tsukamoto, K. ; Nishioka, Y. ; Matsuura, M. ; Eimori, T. ; Inuishi, Masahide ; Miyanaga, I. ; Nakamura, M. ; Kishimoto, T. ; Yamada, T. ; Eriguchi, K. ; Yuasa, H. ; Satake, T. ; Kajiya, A. ; Ogura, M. / Sub-1 μm2 high density embedded SRAM technologies for 100 nm generation SOC and beyond. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2002. pp. 14-15
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