### Abstract

A b-bit SIMD functional unit has n k-bit sub-functional units in itself, where b = k × n. It can execute n-parallel k-bit operations. However, all the b-bit functional units in a processor core do not necessarily execute n-parallel operations. Depending on an application program, some of them just execute n/2-parallel operations or even n/4-parallel operations. This means that we can modify a b-bit SIMD functional unit so that it has n/2 k-bit sub-functional units or n/4 k-bit sub-functional units. The number of k-bit sub-functional units in a SIMD functional unit is called sub-operation parallelism. We incorporate a sub-operation parallelism optimization algorithm into SIMD functional unit optimization. Our proposed algorithm gradually reduces sub-operation parallelism of a SIMD functional unit while the timing constraint of execution time satisfied. Thereby, we can finally find a processor core with small area under the given timing constraint. We expect that we can obtain processor core configurations of smaller area in the same timing constraint rather than a conventional system. The promising experimental results are also shown.

Original language | English |
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Pages (from-to) | 876-883 |

Number of pages | 8 |

Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |

Volume | E88-A |

Issue number | 4 |

DOIs | |

Publication status | Published - 2005 Jan 1 |

### Keywords

- Hardware/software cosynthesis
- Hardware/software partitioning
- Packed SIMD type operation
- Processor synthesis
- Sub-operation parallelism

### ASJC Scopus subject areas

- Signal Processing
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
- Applied Mathematics

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## Cite this

*IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences*,

*E88-A*(4), 876-883. https://doi.org/10.1093/ietfec/e88-a.4.876