Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations

Nozomu Togawa, Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    In this paper, we propose a sub-operation parallelism optimization algorithm in SIMD processor synthesis. Given an initial assembly code and timing constraints, our algorithm synthesizes a processor core with sub-operation parallelism optimization for SIMD functional units. First we consider an initial processor which has sufficient hardware units for executing an initial assembly code. An initial processor core includes the maximum sub-operation parallelism for each SIMD functional unit. By gradually reducing sub-operation parallelism, we can finally have a processor core with small area meeting a given timing constraints. We show the effectiveness of our proposed algorithm through experimental results.

    Original languageEnglish
    Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
    Pages3499-3502
    Number of pages4
    DOIs
    Publication statusPublished - 2005
    EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
    Duration: 2005 May 232005 May 26

    Other

    OtherIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
    CountryJapan
    CityKobe
    Period05/5/2305/5/26

    Fingerprint

    Hardware

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Togawa, N., Kawazu, H., Uchida, J., Miyaoka, Y., Yanagisawa, M., & Ohtsuki, T. (2005). Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 3499-3502). [1465383] https://doi.org/10.1109/ISCAS.2005.1465383

    Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. / Togawa, Nozomu; Kawazu, Hideki; Uchida, Jumpei; Miyaoka, Yuichiro; Yanagisawa, Masao; Ohtsuki, Tatsuo.

    Proceedings - IEEE International Symposium on Circuits and Systems. 2005. p. 3499-3502 1465383.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Togawa, N, Kawazu, H, Uchida, J, Miyaoka, Y, Yanagisawa, M & Ohtsuki, T 2005, Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. in Proceedings - IEEE International Symposium on Circuits and Systems., 1465383, pp. 3499-3502, IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, Kobe, Japan, 05/5/23. https://doi.org/10.1109/ISCAS.2005.1465383
    Togawa N, Kawazu H, Uchida J, Miyaoka Y, Yanagisawa M, Ohtsuki T. Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. In Proceedings - IEEE International Symposium on Circuits and Systems. 2005. p. 3499-3502. 1465383 https://doi.org/10.1109/ISCAS.2005.1465383
    Togawa, Nozomu ; Kawazu, Hideki ; Uchida, Jumpei ; Miyaoka, Yuichiro ; Yanagisawa, Masao ; Ohtsuki, Tatsuo. / Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations. Proceedings - IEEE International Symposium on Circuits and Systems. 2005. pp. 3499-3502
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