Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation

H. Makiyama, Y. Yamamoto, Hirofumi Shinohara, T. Iwamatsu, H. Oda, N. Sugii, K. Ishibashi, T. Mizutani, T. Hiramoto, Y. Yamaguchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation voltage (Vdd). In the ultralow-Vdd regime, however, the upsurging delay (τpd) variability is the most important challenge. This paper proposes the balanced n/p drivability control method for reducing the die-to-die delay variation by back bias applicable for various circuits. Excellent variability reduction by this balanced control is demonstrated at Vdd = 0.4 V.

Original languageEnglish
Title of host publicationTechnical Digest - International Electron Devices Meeting, IEDM
DOIs
Publication statusPublished - 2013
Externally publishedYes
Event2013 IEEE International Electron Devices Meeting, IEDM 2013 - Washington, DC, United States
Duration: 2013 Dec 92013 Dec 11

Other

Other2013 IEEE International Electron Devices Meeting, IEDM 2013
CountryUnited States
CityWashington, DC
Period13/12/913/12/11

Fingerprint

Silicon
Oxides
CMOS
retarding
oxides
Networks (circuits)
Electric potential
electric potential
silicon
Transistors
transistors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Electronic, Optical and Magnetic Materials
  • Materials Chemistry

Cite this

Makiyama, H., Yamamoto, Y., Shinohara, H., Iwamatsu, T., Oda, H., Sugii, N., ... Yamaguchi, Y. (2013). Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation. In Technical Digest - International Electron Devices Meeting, IEDM [6724742] https://doi.org/10.1109/IEDM.2013.6724742

Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation. / Makiyama, H.; Yamamoto, Y.; Shinohara, Hirofumi; Iwamatsu, T.; Oda, H.; Sugii, N.; Ishibashi, K.; Mizutani, T.; Hiramoto, T.; Yamaguchi, Y.

Technical Digest - International Electron Devices Meeting, IEDM. 2013. 6724742.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Makiyama, H, Yamamoto, Y, Shinohara, H, Iwamatsu, T, Oda, H, Sugii, N, Ishibashi, K, Mizutani, T, Hiramoto, T & Yamaguchi, Y 2013, Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation. in Technical Digest - International Electron Devices Meeting, IEDM., 6724742, 2013 IEEE International Electron Devices Meeting, IEDM 2013, Washington, DC, United States, 13/12/9. https://doi.org/10.1109/IEDM.2013.6724742
Makiyama, H. ; Yamamoto, Y. ; Shinohara, Hirofumi ; Iwamatsu, T. ; Oda, H. ; Sugii, N. ; Ishibashi, K. ; Mizutani, T. ; Hiramoto, T. ; Yamaguchi, Y. / Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation. Technical Digest - International Electron Devices Meeting, IEDM. 2013.
@inproceedings{d6dbaa8c10324abf9b1277417531580a,
title = "Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation",
abstract = "Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation voltage (Vdd). In the ultralow-Vdd regime, however, the upsurging delay (τpd) variability is the most important challenge. This paper proposes the balanced n/p drivability control method for reducing the die-to-die delay variation by back bias applicable for various circuits. Excellent variability reduction by this balanced control is demonstrated at Vdd = 0.4 V.",
author = "H. Makiyama and Y. Yamamoto and Hirofumi Shinohara and T. Iwamatsu and H. Oda and N. Sugii and K. Ishibashi and T. Mizutani and T. Hiramoto and Y. Yamaguchi",
year = "2013",
doi = "10.1109/IEDM.2013.6724742",
language = "English",
isbn = "9781479923076",
booktitle = "Technical Digest - International Electron Devices Meeting, IEDM",

}

TY - GEN

T1 - Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation

AU - Makiyama, H.

AU - Yamamoto, Y.

AU - Shinohara, Hirofumi

AU - Iwamatsu, T.

AU - Oda, H.

AU - Sugii, N.

AU - Ishibashi, K.

AU - Mizutani, T.

AU - Hiramoto, T.

AU - Yamaguchi, Y.

PY - 2013

Y1 - 2013

N2 - Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation voltage (Vdd). In the ultralow-Vdd regime, however, the upsurging delay (τpd) variability is the most important challenge. This paper proposes the balanced n/p drivability control method for reducing the die-to-die delay variation by back bias applicable for various circuits. Excellent variability reduction by this balanced control is demonstrated at Vdd = 0.4 V.

AB - Small-variability transistors such as silicon on thin buried oxide (SOTB) are effective for reducing the operation voltage (Vdd). In the ultralow-Vdd regime, however, the upsurging delay (τpd) variability is the most important challenge. This paper proposes the balanced n/p drivability control method for reducing the die-to-die delay variation by back bias applicable for various circuits. Excellent variability reduction by this balanced control is demonstrated at Vdd = 0.4 V.

UR - http://www.scopus.com/inward/record.url?scp=84894329474&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84894329474&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2013.6724742

DO - 10.1109/IEDM.2013.6724742

M3 - Conference contribution

AN - SCOPUS:84894329474

SN - 9781479923076

BT - Technical Digest - International Electron Devices Meeting, IEDM

ER -